Compiler-assisted instruction decoder energy optimization for clustered VLIW architectures

Traditionally, an instruction decoder is designed as a monolithic structure that inhibit the leakage energy optimization. In this paper, we consider a split instruction decoder that enable the leakage energy optimization. We also propose a compiler scheduling algorithm that exploits instruction slack to increase the simultaneous active and idle duration in instruction decoder. The proposed compiler-assisted scheme obtains a further 14.5% reduction of energy consumption of instruction decoder over a hardware-only scheme for a VLIW architecture. The benefits are 17.3% and 18.7% in the context of a 2-clustered and a 4-clustered VLIW architecture respectively.

Chemically Programmed Ultrahigh Density Two-Dimensional Semiconductor Superlattice Array

Designing an ultrahigh density linear superlattice array consisting of periodic blocks of different semiconductors in the strong confinement regime via a direct synthetic route remains an unachieved challenge in nanotechnology. We report a general synthesis route for the formulation of a large-area ultrahigh density superlattice array that involves adjoining multiple units of ZnS rods by prolate US particles at the tips. A single one-dimensional wire is 300-500 nm long and consists of periodic quantum wells with a barrier width of 5 nm provided by ZnS and a well width of 1-2 nm provided by CdS, defining a superlattice structure. The synthesis route allows for tailoring of ultranarrow laserlike emissions (fwhm approximate to 125 meV) originating from strong interwell energy dispersion along with control of the width, pitch, and registry of the superlattice assembly. Such an exceptional high-density superlattice array could form the basis of ultrahigh density memories in addition to offering opportunities for technological advancement in conventional heterojunction-based device applications.

Design and fabrication of an automated temperature programmed reaction system to evaluate 3-way catalysts Ce1-x-y(La/Y)(x)PtyO2-delta

A completely automated temperature-programmed reaction (TPR) system for carrying out gas-solid catalytic reactions under atmospheric flow conditions is fabricated to study CO and hydrocarbon oxidation, and NO reduction. The system consists of an all-stainless steel UHV system, quadrupole mass spectrometer SX200 (VG Scientific), a tubular furnace and micro-reactor, a temperature controller, a versatile gas handling system, and a data acquisition and analysis system. The performance of the system has been tested under standard experimental conditions for CO oxidation over well-characterized Ce1-x-y(La/Y)(y)O2-delta catalysts. Testing of 3-way catalysis with CO, NO and C2H2 to convert to CO2, N-2 and H2O is done with this catalyst which shows complete removal of pollutants below 325 degrees C. Fixed oxide-ion defects in Pt substituted Ce1-y(La/Y)(y)O2-y/2 show higher catalytic activity than Pt ion-substituted CeO2

Design and fabrication of an automated temperature programmed reaction system to evaluate 3-way catalysts Ce1-x-y(La/Y)(x)PtyO2-delta

A completely automated temperature-programmed reaction (TPR) system for carrying out gas-solid catalytic reactions under atmospheric flow conditions is fabricated to study CO and hydrocarbon oxidation, and NO reduction. The system consists of an all-stainless steel UHV system, quadrupole mass spectrometer SX200 (VG Scientific), a tubular furnace and micro-reactor, a temperature controller, a versatile gas handling system, and a data acquisition and analysis system. The performance of the system has been tested under standard experimental conditions for CO oxidation over well-characterized Ce1-x-y(La/Y)(y)O2-delta catalysts. Testing of 3-way catalysis with CO, NO and C2H2 to convert to CO2, N-2 and H2O is done with this catalyst which shows complete removal of pollutants below 325 degrees C. Fixed oxide-ion defects in Pt substituted Ce1-y(La/Y)(y)O2-y/2 show higher catalytic activity than Pt ion-substituted CeO2.

Signaling different pathways of cell death: Abrin induced programmed necrosis in U266B1 cells

Abrin is a type II ribosome-inactivating protein comprising of two subunits, A and B. Of the two, the A-subunit harbours the RNA-N-glycosidase activity and the B subunit is a galactose specific lectin that enables the entry of the protein inside the cell. Abrin inhibits protein synthesis and has been reported to induce apoptosis in several cell types. Based on these observations abrin is considered to have potential for the construction of immunotoxin in cell targeted therapy. Preliminary data from our laboratory however showed that although abrin inhibited the protein synthesis in all cell types, the mode of cell death varied. The aim of the present study was therefore to understand different death pathways induced by abrin in different cells. We used the human B cell line, U266B1 and compared it with the earlier studied T cell line Jurkat, for abrin-mediated inhibition of protein translation as well as cell death. While abrin triggered programmed apoptosis in Jurkat cells in a caspase-dependent manner, it induced programmed necrosis in U266B1 cells in a caspase-independent manner, even when there was reactive oxygen species production and loss of mitochondrial membrane potential. The data revealed that abrin-mediated necrosis involves lysosomal membrane permeabilization and release of cathepsins from the lysosomes. Importantly, the choice of abrin-mediated death pathway in the cells appears to depend on which of the two events occurs first: lysosomal membrane permeabilization or loss of mitochondrial membrane potential that decides cell death by necrosis or apoptosis. (C) 2010 Elsevier Ltd. All rights reserved.

Temperature-programmed desorption and surface reaction of thiophene over co-mo/.gamma.-Al2O3 hydrodesulfurization catalysts

The temperature-programmed desorption (TPD) and temperature-programmed surface reaction (TPSR) of thiophene over a series of Co-Mo/gamma-Al2O3, hydrodesulfurization (HDS) catalysts with varying Co to Mo ratios have been studied with the objective of understanding the promotional role of Co in the HDS reaction. As part of the study, the desorptions (TPD) and hydrogenations (TPSR) of butane, butene, and butadiene over these catalysts have also been investigated. The TPD of the hydrocarbons over catalysts containing no Co showed a single desorption profile while incorporation of Co created an additional site, with higher heats of desorption, without significantly affecting desorption from the original site. The TPSR measurements showed that the two sites had separate and independent activity for the hydrogenation of the C-4 hydrocarbons. The TPD of thiophene over catalysts with varying Co to Mo ratios showed a single desorption profile with identical heats of desorption, implying that Co does not affect or influence the adsorption sites for thiophene. The TPSR of the HDS of thiophene, however, showed that, although the products of the HDS reaction-butane, butene, and H2S-are the same irrespective of the Co content, the temperature profiles and the activation barriers for the formation of these species show considerable change with the Co/Co+Mo ratio. The results are discussed in light of the existing models for the promotional role of Co in the HDS reaction.

Temperature programmed desorption studies on hydrodesulfurization catalysts

The temperature programmed-desorption (TPD) of butane, butene, butadiene and thiophene over a series of Co-MO/gamma-Al2O3 catalysts with varying Co to Mo ratio has been investigated. The TPD of butane, butene and butadiene over catalysts containing no Co showed a single desorption profile while incorporation of Co created an additional site without significantly affecting desorption from the original site. The TPD of thiophene over a series of catalysts with varying Co content showed identical desorption temperature as well as heat of desorption. It was concluded that thiophene was adsorbed on the ''Mo-S'' component of the catalyst and was unaffected by the presence of Co.

Methanol-to-gasoline (MTG) conversion over ZSM-5. A temperature programmed surface reaction study

The conversion of methanol to gasoline over zeolite ZSM-5 has been studied by temperature programmed surface reaction (TPSR). The technique is able to monitor the two steps in the process: the dehydration of methanol to dimethyl ether and the subsequent conversion of dimethyl ether to hydrocarbons. The activation barriers associated with each step were evaluated from the TPSR profiles and are 25.7 and 46.5 kcal/mol respectively. The methanol desorption profile shows considerable change with the amount of methanol molecules adsorbed per Bronsted site of the zeolite. The energy associated with the desorption process, (CH3OHH+-ZSM5 --> (CH3OHH+-ZSM5 + CH3OH, shows a spectrum of values depending on n.

A Scalable Low Power Issue Queue for Large Instruction Window Processors

Large instruction windows and issue queues are key to exploiting greater instruction level parallelism in out-of-order superscalar processors. However, the cycle time and energy consumption of conventional large monolithic issue queues are high. Previous efforts to reduce cycle time segment the issue queue and pipeline wakeup. Unfortunately, this results in significant IPC loss. Other proposals which address energy efficiency issues by avoiding only the unnecessary tag-comparisons do not reduce broadcasts. These schemes also increase the issue latency.To address both these issues comprehensively, we propose the Scalable Lowpower Issue Queue (SLIQ). SLIQ augments a pipelined issue queue with direct indexing to mitigate the problem of delayed wakeups while reducing the cycle time. Also, the SLIQ design naturally leads to significant energy savings by reducing both the number of tag broadcasts and comparisons required.A 2 segment SLIQ incurs an average IPC loss of 0.2% over the entire SPEC CPU2000 suite, while achieving a 25.2% reduction in issue latency when compared to a monolithic 128-entry issue queue for an 8-wide superscalar processor. An 8 segment SLIQ improves scalability by reducing the issue latency by 38.3% while incurring an IPC loss of only 2.3%. Further, the 8 segment SLIQ significantly reduces the energy consumption and energy-delay product by 48.3% and 67.4% respectively on average.

Improving Superscalar Instruction Dispatch And Issue By Exploiting Dynamic Code Sequences

Superscalar processors currently have the potential to fetch multiple basic blocks per cycle by employing one of several recently proposed instruction fetch mechanisms. However, this increased fetch bandwidth cannot be exploited unless pipeline stages further downstream correspondingly improve. In particular,register renaming a large number of instructions per cycle is diDcult. A large instruction window, needed to receive multiple basic blocks per cycle, will slow down dependence resolution and instruction issue. This paper addresses these and related issues by proposing (i) partitioning of the instruction window into multiple blocks, each holding a dynamic code sequence; (ii) logical partitioning of the registerjle into a global file and several local jles, the latter holding registers local to a dynamic code sequence; (iii) the dynamic recording and reuse of register renaming information for registers local to a dynamic code sequence. Performance studies show these mechanisms improve performance over traditional superscalar processors by factors ranging from 1.5 to a little over 3 for the SPEC Integer programs. Next, it is observed that several of the loops in the benchmarks display vector-like behavior during execution, even if the static loop bodies are likely complex for compile-time vectorization. A dynamic loop vectorization mechanism that builds on top of the above mechanisms is briefly outlined. The mechanism vectorizes up to 60% of the dynamic instructions for some programs, albeit the average number of iterations per loop is quite small.

Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation

Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an optimizing compiler, they do not succeed many a time due to limited knowledge of run-time data. In this paper we examine instruction reuse of integer ALU and load instructions in network processing applications. Specifically, this paper attempts to answer the following questions: (1) How much of instruction reuse is inherent in network processing applications?, (2) Can reuse be improved by reducing interference in the reuse buffer?, (3) What characteristics of network applications can be exploited to improve reuse?, and (4) What is the effect of reuse on resource contention and memory accesses? We propose an aggregation scheme that combines the high-level concept of network traffic i.e. "flows" with a low level microarchitectural feature of programs i.e. repetition of instructions and data along with an architecture that exploits temporal locality in incoming packet data to improve reuse. We find that for the benchmarks considered, 1% to 50% of instructions are reused while the speedup achieved varies between 1% and 24%. As a side effect, instruction reuse reduces memory traffic and can therefore be considered as a scheme for low power.

Relative roles of instruction count and cycles per instruction in WCET estimation

Most of the existing WCET estimation methods directly estimate execution time, ET, in cycles. We propose to study ET as a product of two factors, ET = IC * CPI, where IC is instruction count and CPI is cycles per instruction. Considering directly the estimation of ET may lead to a highly pessimistic estimate since implicitly these methods may be using worst case IC and worst case CPI. We hypothesize that there exists a functional relationship between CPI and IC such that CPI=f(IC). This is ascertained by computing the covariance matrix and studying the scatter plots of CPI versus IC. IC and CPI values are obtained by running benchmarks with a large number of inputs using the cycle accurate architectural simulator, Simplescalar on two different architectures. It is shown that the benchmarks can be grouped into different classes based on the CPI versus IC relationship. For some benchmarks like FFT, FIR etc., both IC and CPI are almost a constant irrespective of the input. There are other benchmarks that exhibit a direct or an inverse relationship between CPI and IC. In such a case, one can predict CPI for a given IC as CPI=f(IC). We derive the theoretical worst case IC for a program, denoted as SWIC, using integer linear programming(ILP) and estimate WCET as SWIC*f(SWIC). However, if CPI decreases sharply with IC then measured maximum cycles is observed to be a better estimate. For certain other benchmarks, it is observed that the CPI versus IC relationship is either random or CPI remains constant with varying IC. In such cases, WCET is estimated as the product of SWIC and measured maximum CPI. It is observed that use of the proposed method results in tighter WCET estimates than Chronos, a static WCET analyzer, for most benchmarks for the two architectures considered in this paper.