44 resultados para Power factor corrections

em Indian Institute of Science - Bangalore - Índia


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This paper describes a method of adjusting the stator power factor angle for the control of an induction motor fed from a current source inverter (CSI) based on the concept of space vectors (or park vectors). It is shown that under steady state, if the torque angle is kept constant over the entire operating range, it has the advantage of keeping the slip frequency constant. This can be utilized to dispose of the speed feedback and simplify the control scheme for the drive, such that the stator voltage integral zero crossings alone can be used as a feedback for deciding the triggering instants of the CSI thyristors under stable operation of the system. A closed-loop control strategy is developed for the drive based on this principle, using a microprocessor-based control system and is implemented on a laboratory prototype CSI fed induction motor drive.

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This paper proposes a method of sharing power/energy between multiple sources and multiple loads using an integrated magnetic circuit as a junction between sources and sinks. It also presents a particular use of the magnetic circuit as an ac power supply, delivering sinusoidal voltage to load irrespective of the presence of the grid, taking only active power from the grid. The proposed magnetic circuit is a three-energy-port unit, viz.: 1) power/energy from grid; 2) power energy from battery-inverter unit; and 3) power/energy delivery to the load in its particular application as quality ac power supply (QPS). The product provides sinusoidal regulated output voltage, input power-factor correction, electrical isolation between the sources and loads, low battery voltage, and control simplicity. Unlike conventional series-shunt-compensated uninterruptible power supply topologies with low battery voltage, the isolation is provided using a single magnetic circuit that results in a smaller size and lower cost. The circuit operating principles and analysis, as well as simulation and experimental results, are presented for this QPS.

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This paper provides additional theoretical information on half-wave-length power transmission. The analysis is rendered more general by consideration of a natural half-wave line instead of a short line tuned to half-wave. The effects of line loading and its power factor on the voltage and current profiles of the line and ganerator excitation have been included. Some of the operating problems such as charging of the line and synchronization of the half-wave system are also discussed. The inevitability of power-frequency overvoltages during faults is established. Stability studies have indicated that the use of switching stations is not beneficial. Typical swing curves are also presented.

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This paper presents an analysis and comparison between two circuit topologies of the 3-phase, 3-level unity power factor (Vienna) rectifier on the basis of packaging issues and semiconductor power losses. The analysis indicates the suitability of one particular circuit variant due to restrictions on switching frequency at higher power levels. A comparison is also done between hysteresis and carrier based PWM strategies for current control of the rectifier, along with experimental evaluation of the control strategies on a hardware prototype of the rectifier. The comparison indicates that the carrier based modulation strategy is better suited for use with higher order filters that are utilized in high power applications.

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This paper presents the design of a start up power circuit for a control power supply (CPS) which feeds power to the sub-systems of High Power Converters (HPC). The sub-systems such as gate drive card, annunciation card, protection and delay card etc; needs to be provided power for the operation of a HPC. The control power supply (CPS) is designed to operate over a wide range of input voltage from 90Vac to 270Vac. The CPS output supplies power at a desired voltage of Vout =24V to the auxiliary sub-systems of the HPC. During the starting, the power supply to the control circuitry of CPS in turn, is obtained using a separate start-up power supply. This paper discusses the various design issues of the start-up power circuit to ensure that start-up and shut down of the CPS occurs reliably. The CPS also maintains the power factor close to unity and low total harmonic distortion in input current. The paper also provides design details of gate drive circuits employed for the CPS as well as the design of on-board power supply for the CPS. Index terms: control power supply, start-up power supply, DSFC, pre-regulator

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Current source inverter (CSI) is an attractive solution in high-power drives. The conventional gate turn-off thyristor (GTO) based CSI-fed induction motor drives suffer from drawbacks such as low-frequency torque pulsation, harmonic heating, and unstable operation at low-speed ranges. These drawbacks can be overcome by connecting a current-controlled voltage source inverter (VSI) across the motor terminal replacing the bulky ac capacitors. The VSI provides the harmonic currents, which results in sinusoidal motor voltage and current even with the CSI switching at fundamental frequency. This paper proposes a CSI-fed induction motor drive scheme where GTOs are replaced by thyristors in the CSI without any external circuit to assist the turning off of the thyristors. Here, the current-controlled VSI, connected in shunt, is designed to supply the volt ampere reactive requirement of the induction motor, and the CSI is made to operate in leading power factor mode such that the thyristors in the CSI are autosequentially turned off. The resulting drive will be able to feed medium-voltage, high-power induction motors directly. A sensorless vector-controlled CSI drive based on the proposed configuration is developed. The experimental results from a 5 hp prototype are presented. Experimental results show that the proposed drive has stable operation throughout the operating range of speeds.

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Thyristor forced commutated AC/DC convertors are useful for improving the power factor and waveform of AC-side line current. These are controlled through pulse-width modulation schemes for best performance. However, the 3-phase versions impose restrictions on the PWM strategies that can be implemented for excellent harmonic rejection. This paper presents new PWM control strategies for the 3-phase converters and compares them along with the conventional 4-pulse PWM strategy for harmonic elimination. Finally, two new PWM strategies are shown to be the best, for which oscillograms are presented from actual implementation.

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A simple multiple pulsewidth modulated (MPWM) ac chopper using power transistors for 3-ý power control is discussed. 120ý chopping period is used for main transistors so that the circuit can accommodate resistive and lagging or leading power factor loads. Only 1-ý sensing is used for 3-ý control. An alternate economical power and control schemes for 3-ý MPWM ac choppers suitable only for resistive loads is also suggested. The experimental results for 12 choppings per cycle are given.

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A simple multiple pulsewidth modulated (MPWM) ac chopper using power transistors for 3-¿ power control is discussed. 120° chopping period is used for main transistors so that the circuit can accommodate resistive and lagging or leading power factor loads. Only 1-¿ sensing is used for 3-¿ control. An alternate economical power and control schemes for 3-¿ MPWM ac choppers suitable only for resistive loads is also suggested. The experimental results for 12 choppings per cycle are given.

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This paper proposes a control method that can balance the input currents of the three-phase three-wire boost rectifier under unbalanced input voltage condition. The control objective is to operate the rectifier in the high-power-factor mode under balanced input voltage condition but to give overriding priority to the current balance function in case of unbalance in the input voltage. The control structure has been divided into two major functional blocks. The inner loop current-mode controller implements resistor emulation to achieve high-power-factor operation on each of the two orthogonal axes of the stationary reference frame. The outer control loop performs magnitude scaling and phase-shifting operations on current of one of the axes to make it balanced with the current on the other axis. The coefficients of scaling and shifting functions are determined by two closed-loop prportional-integral (PI) controllers that impose the conditions of input current balance as PI references. The control algorithm is simple and high performing. It does not require input voltage sensing and transformation of the control variables into a rotating reference frame. The simulation results on a MATLAB-SIMULINK platform validate the proposed control strategy. In implementation Texas Instrument's digital signal processor TMS320F24OF is used as the digital controller. The control algorithm for high-power-factor operation is tested on a prototype boost rectifier under nominal and unbalanced input voltage conditions.

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A simple, low-cost, constant frequency, analog controller is proposed for the front-end half-bridge rectifier of a single-phase transformerless UPS system to maintain near unity power factor at the input and zero dc-offset voltage at the output. The controller generates the required gating pulses by comparing the input current with a periodic, bipolar, linear carrier without sensing the input voltage. Two voltage controllers and a single integrator with reset are used to generate the required carrier. All the necessary control operations can be performed without using any PLL, multiplier and/or divider. The controller can be fabricated as a single integrated circuit. The control concept is validated through simulation and also experimentally on an 800W half-bridge rectifier. Experimental results are presented for ac-dc application, and also for ac-dc-ac UPS application with both sinusoidal and nonlinear loads. The simulation and experimental results agree well.

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Neutral point clamped (NPC), three level converters with insulated gate bipolar transistor devices are very popular in medium voltage, high power applications. DC bus short circuit protection is usually done, using the sensed voltage across collector and emitter (i.e., V-CE sensing), of all the devices in a leg. This feature is accommodated with the conventional gate drive circuits used in the two level converters. The similar gate drive circuit, when adopted for NPC three level converter protection, leads to false V-CE fault signals for inner devices of the leg. The paper explains the detailed circuit behavior and reasons, which result in the occurrence of such false V-CE fault signals. This paper also illustrates that such a phenomenon shows dependence on the power factor of the supplied three-phase load. Finally, experimental results are presented to support the analysis. It is shown that the problem can be avoided by blocking out the V-CE sense fault signals of the inner devices of the leg.

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Till date load-commutated inverter (LCI)-fed synchronous motor drive configuration is popular in high power applications (>10 MW). The leading power factor operation of synchronous motor by excitation control offers this simple and rugged drive structure. On the contrary, LCI-fed induction motor drive is absent as it always draws lagging power factor current. Therefore, complicated commutation circuit is required to switch off thyristors for a current source inverter (CSI)-driven induction motor. It poses the major hindrance to scale up the power rating of CSI-fed induction motor drive. Anew power topology for LCI-fed induction motor drive for medium-voltage drive application is proposed. A new induction machine (active-reactive induction machine) with two sets of three-phase winding is introduced as a drive motor. The proposed power configuration ensures sinusoidal voltage and current at the motor terminals. The total drive power is shared among a thyristor-based LCI, an insulated gate bipolar transistor (IGBT)-based two-level voltage source inverter (VSI), and a three-level VSI. The benefits of SCRs and IGBTs are explored in the proposed drive. Experimental results from a prototype drive verify the basic concepts of the drive.

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In this paper, a new three-phase, five-level inverter topology with a single-dc source is presented. The proposed topology is obtained by cascading a three-level flying capacitor inverter with a flying H-bridge power cell in each phase. This topology has redundant switching states for generating different pole voltages. By selecting appropriate switching states, the capacitor voltages can be balanced instantaneously (as compared to the fundamental) in any direction of the current, irrespective of the load power factor. Another important feature of this topology is that if any H-bridge fails, it can be bypassed and the configuration can still operate as a three-level inverter at its full power rating. This feature improves the reliability of the circuit. A 3-kW induction motor is run with the proposed topology for the full modulation range. The effectiveness of the capacitor balancing algorithm is tested for the full range of speed and during the sudden acceleration of the motor.

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This study proposes an inverter circuit topology capable of generating multilevel dodecagonal (12-sided polygon) voltage space vectors by the cascaded connection of two-level and three-level inverters. By the proper selection of DC-link voltages and resultant switching states for the inverters, voltage space vectors whose tips lie on three concentric dodecagons, are obtained. A rectifier circuit for the inverter is also proposed, which significantly improves the power factor. The topology offers advantages such as the complete elimination of the fifth and seventh harmonics in phase voltages and an extension of the linear modulation range. In this study, a simple method for the calculation of pulse width modulation timing was presented along with extensive simulation and experimental results in order to validate the proposed concept.