MPI-based parallel synchronous vector evaluated particle swarm optimization for multi-objective design optimization of composite structures

This paper presents a decentralized/peer-to-peer architecture-based parallel version of the vector evaluated particle swarm optimization (VEPSO) algorithm for multi-objective design optimization of laminated composite plates using message passing interface (MPI). The design optimization of laminated composite plates being a combinatorially explosive constrained non-linear optimization problem (CNOP), with many design variables and a vast solution space, warrants the use of non-parametric and heuristic optimization algorithms like PSO. Optimization requires minimizing both the weight and cost of these composite plates, simultaneously, which renders the problem multi-objective. Hence VEPSO, a multi-objective variant of the PSO algorithm, is used. Despite the use of such a heuristic, the application problem, being computationally intensive, suffers from long execution times due to sequential computation. Hence, a parallel version of the PSO algorithm for the problem has been developed to run on several nodes of an IBM P720 cluster. The proposed parallel algorithm, using MPI's collective communication directives, establishes a peer-to-peer relationship between the constituent parallel processes, deviating from the more common master-slave approach, in achieving reduction of computation time by factor of up to 10. Finally we show the effectiveness of the proposed parallel algorithm by comparing it with a serial implementation of VEPSO and a parallel implementation of the vector evaluated genetic algorithm (VEGA) for the same design problem. (c) 2012 Elsevier Ltd. All rights reserved.

An efficient design of serial and parallel memory using Quantum dot cellular automata

Quantum cellular automata (QCA) is a new technology in the nanometer scale and has been considered as one of the alternative to CMOS technology. In this paper, we describe the design and layout of a serial memory and parallel memory, showing the layout of individual memory cells. Assuming that we can fabricate cells which are separated by 10nm, memory capacities of over 1.6 Gbit/cm2 can be achieved. Simulations on the proposed memories were carried out using QCADesigner, a layout and simulation tool for QCA. During the design, we have tried to reduce the number of cells as well as to reduce the area which is found to be 86.16sq mm and 0.12 nm2 area with the QCA based memory cell. We have also achieved an increase in efficiency by 40%.These circuits are the building block of nano processors and provide us to understand the nano devices of the future.

SHAMP: An experimental shared memory multimicroprocessor system for performance evaluation of parallel algorithms

In this paper, the design and implementation of a single shared bus, shared memory multiprocessing system using Intel's single board computers is presented. The hardware configuration and the operating system developed to execute the parallel algorithms are discussed. The performance evaluation studies carried out on Image are outlined.

A study on bullock carts. Part 1. Engineering analysis of the two-wheel bullock cart design

An engineering analysis of the design of two-wheel bullock carts has been carried out with the aid of a mathematical model. Non-dimensional expressions for the pull and the neck load have been developed. In the first instance, the cart is assumed to be cruising at constant velocity on a terrain with the effective coefficient of rolling friction varying over a wide range (0.001 to 0.5) and the gradient varying between +0.2 to −0.2. Subsequently, the effect of inertia force due to an acceleration parallel to the ground is studied. In the light of this analysis, two modifications to the design of the cart have been proposed and the relative merits of the current designs and the proposed designs are discussed.

Design of a synchronous decade down counter

Digital positioning systems often require a down counter for their operation. Due to the necessity of particular logic sequences and control of individual terminals, the design of down counters for particular use is very essential. In this paper the design procedure and logic diagram for a synchronous decade down counter with parallel carry are presented.

An algebraic formulation of static isotropy and design of statically isotropic 6-6 Stewart platform manipulators

In this paper, we present an algebraic method to study and design spatial parallel manipulators that demonstrate isotropy in the force and moment distributions. We use the force and moment transformation matrices separately, and derive conditions for their isotropy individually as well as in combination. The isotropy conditions are derived in closed-form in terms of the invariants of the quadratic forms associated with these matrices. The formulation is applied to a class of Stewart platform manipulator, and a multi-parameter family of isotropic manipulators is identified analytically. We show that it is impossible to obtain a spatially isotropic configuration within this family. We also compute the isotropic configurations of an existing manipulator and demonstrate a procedure for designing the manipulator for isotropy at a given configuration. (C) 2008 Elsevier Ltd. All rights reserved.

Optimum design of cantilever sheet pile walls in sandy soils using inverse reliability approach

In this paper an approach for obtaining depth and section modulus of the cantilever sheet pile wall using inverse reliability method is described. The proposed procedure employs inverse first order reliability method to obtain the design penetration depth and section modulus of the steel sheet pile wall in order that the reliability of the wall against failure modes must meet a desired level of safety. Sensitivity analysis is conducted to assess the effect of uncertainties in design parameters on the reliability of cantilever sheet pile walls. The analysis is performed by treating back fill soil properties, depth of the water table from the top of the sheet pile wall, yield strength of steel and section modulus of steel pile as random variables. Two limit states, viz., rotational and flexural failure of sheet pile wall are considered. The results using this approach are used to develop a set of reliability based design charts for different coefficients of variation of friction angle of the backfill (5%, 10% and 15%). System reliability considerations in terms of series and parallel systems are also studied.

Parallel implementation of AutoDock

Computational docking of ligands to protein structures is a key step in structure-based drug design. Currently, the time required for each docking run is high and thus limits the use of docking in a high-throughput manner, warranting parallelization of docking algorithms. AutoDock, a widely used tool, has been chosen for parallelization. Near-linear increases in speed were observed with 96 processors, reducing the time required for docking ligands to HIV-protease from 81 min, as an example, on a single IBM Power-5 processor ( 1.65 GHz), to about 1 min on an IBM cluster, with 96 such processors. This implementation would make it feasible to perform virtual ligand screening using AutoDock.

BER-optimized linear parallel interference cancellers for multicarrier DS-CDMA systems

In this paper, we consider the design and bit-error performance analysis of linear parallel interference cancellers (LPIC) for multicarrier (MC) direct-sequence code division multiple access (DS-CDMA) systems. We propose an LPIC scheme where we estimate and cancel the multiple access interference (MAT) based on the soft decision outputs on individual subcarriers, and the interference cancelled outputs on different subcarriers are combined to form the final decision statistic. We scale the MAI estimate on individual subcarriers by a weight before cancellation. In order to choose these weights optimally, we derive exact closed-form expressions for the bit-error rate (BER) at the output of different stages of the LPIC, which we minimize to obtain the optimum weights for the different stages. In addition, using an alternate approach involving the characteristic function of the decision variable, we derive BER expressions for the weighted LPIC scheme, matched filter (MF) detector, decorrelating detector, and minimum mean square error (MMSE) detector for the considered multicarrier DS-CDMA system. We show that the proposed BER-optimized weighted LPIC scheme performs better than the MF detector and the conventional LPIC scheme (where the weights are taken to be unity), and close to the decorrelating and MMSE detectors.

Free convection heat transfer between vertical parallel plates

A new mathematical model for the solution of the problem of free convection heat transfer between vertical parallel flat isothermal plates under isothermal boundary conditions, has been presented. The set of boundary layer equations used in the model are transformed to nonlinear coupled differential equations by similarity type variables as obtained by Ostrach for vertical flat plates in an infinite fluid medium. By utilising a parameter ηw* to represent the outer boundary, the governing differential equations are solved numerically for parametric values of Pr = 0.733. 2 and 3, and ηw* = 0.1, 0.5, 1, 2, 3, 4, ... and 8.0. The velocity and temperature profiles are presented. Results indicate that ηw* can effectively classify the system into (1) thin layers where conduction predominates, (2) intermediate layers and (3) thick layers whose results can be predicted by the solutions for vertical flat plates in infinite fluid medium. Heat transfer correlations are presented for the 3 categories. Several experimental and analytical results available in the literature agree with the present correlations.

Parallel circuit partitioning on a reduced array architecture

The physical design of a VLSI circuit involves circuit partitioning as a subtask. Typically, it is necessary to partition a large electrical circuit into several smaller circuits such that the total cross-wiring is minimized. This problem is a variant of the more general graph partitioning problem, and it is known that there does not exist a polynomial time algorithm to obtain an optimal partition. The heuristic procedure proposed by Kernighan and Lin1,2 requires O(n2 log2n) time to obtain a near-optimal two-way partition of a circuit with n modules. In the VLSI context, due to the large problem size involved, this computational requirement is unacceptably high. This paper is concerned with the hardware acceleration of the Kernighan-Lin procedure on an SIMD architecture. The proposed parallel partitioning algorithm requires O(n) processors, and has a time complexity of O(n log2n). In the proposed scheme, the reduced array architecture is employed with due considerations towards cost effectiveness and VLSI realizability of the architecture.The authors are not aware of any earlier attempts to parallelize a circuit partitioning algorithm in general or the Kernighan-Lin algorithm in particular. The use of the reduced array architecture is novel and opens up the possibilities of using this computing structure for several other applications in electronic design automation.

Groove Binding Ligands for the Interaction with Parallel-Stranded ps-Duplex DNA and Triplex DNA

DNA adopts different conformations not only based on novel base pairs, but also with different chain polarities. Besides several duplex structures (A, B, Z, parallel stranded (ps)-DNA, etc.), DNA also forms higher-order structures like triplex, tetraplex, and i-motif. Each of these structures has its own biological significance. The ps-duplexes have been found to be resistant to certain nucleases and endonucleases. Molecules that promote triple-helix formation have significant potential. These investigations have many therapeutic advantages which may be useful in the regulation of the expression of genes responsible for certain diseases by locking either their transcription (antigene) or translation (antisense). Each DNA minor groove binding ligand (MGBL) interacts with DNA through helical minor groove recognition in a sequence-specific manner, and this interferes with several DNA-associated processes. Incidentally, these ligands interact with some non-B-DNA and with higher-order DNA structures including ps-DNA and triplexes. While the design and recognition of minor grooves of duplex DNA by specific MGBLs have been a topic of many reports, limited information is available on the binding behavior of MGBLs with nonduplex DNA. In this review, we summarize various attempts of the interaction of MGBLs with ps-DNA and DNA triplexes.

Design and performance evaluation of a systolic architecture for hidden-surface removal

In this paper, we propose a systolic architecture for hidden-surface removal. Systolic architecture is a kind of parallel architecture best known for its easy VLSI implementability. After discussing the design details of the architecture, we present the results of the simulation experiments conducted in order to evaluate the performance of the architecture.

Artificial Bee Colony (ABC) for multi-objective design optimization of composite structures

In this paper, we present a generic method/model for multi-objective design optimization of laminated composite components, based on Vector Evaluated Artificial Bee Colony (VEABC) algorithm. VEABC is a parallel vector evaluated type, swarm intelligence multi-objective variant of the Artificial Bee Colony algorithm (ABC). In the current work a modified version of VEABC algorithm for discrete variables has been developed and implemented successfully for the multi-objective design optimization of composites. The problem is formulated with multiple objectives of minimizing weight and the total cost of the composite component to achieve a specified strength. The primary optimization variables are the number of layers, its stacking sequence (the orientation of the layers) and thickness of each layer. The classical lamination theory is utilized to determine the stresses in the component and the design is evaluated based on three failure criteria: failure mechanism based failure criteria, maximum stress failure criteria and the tsai-wu failure criteria. The optimization method is validated for a number of different loading configurations-uniaxial, biaxial and bending loads. The design optimization has been carried for both variable stacking sequences, as well fixed standard stacking schemes and a comparative study of the different design configurations evolved has been presented. Finally the performance is evaluated in comparison with other nature inspired techniques which includes Particle Swarm Optimization (PSO), Artificial Immune System (AIS) and Genetic Algorithm (GA). The performance of ABC is at par with that of PSO, AIS and GA for all the loading configurations. (C) 2009 Elsevier B.V. All rights reserved.

Design of nonequivalent self-routing networks based on a matrix model

In earlier work, nonisomorphic graphs have been converted into networks to realize Multistage Interconnection networks, which are topologically nonequivalent to the Baseline network. The drawback of this technique is that these nonequivalent networks are not guaranteed to be self-routing, because each node in the graph model can be replaced by a (2 × 2) switch in any one of the four different configurations. Hence, the problem of routing in these networks remains unsolved. Moreover, nonisomorphic graphs were obtained by interconnecting bipartite loops in a heuristic manner; the heuristic nature of this procedure makes it difficult to guarantee full connectivity in large networks. We solve these problems through a direct approach, in which a matrix model for self-routing networks is developed. An example is given to show that this model encompases nonequivalent self-routing networks. This approach has the additional advantage in that the matrix model itself ensures full connectivity.