Quaternary adder, subtractor and multiplier using quaternary multiplexer

Multiplexers, as in the case of binary, are very useful building blocks in the development of quaternary systems. The use of quaternary multiplexer (QMUX) in the implementation of quaternary adder, subtractor and multiplier is described in this paper. Quaternary coded decimal (QCD) adder/subtractor and quaternary excess-3 adder/subtractor realization using QMUX are also proposed

Ternary adder and subtracter using ternary multiplexer

This paper describes the use of a ternary multiplexer as a building block in the implementation of ternary adders and subtractors and also in the development of ternary coded adders/subtractors.

Quaternary unary operators

Unary operators are functions of a single variable. Realization of quaternary unary operators (QUOs) using quaternary multiplexer (QMUX) is presented in this paper. QUOs are divided into eight groups on the basis of the number of change overs in the output for an input sequence of 0, 1, 2, 3. This grouping reduces the hardware required to realize them. QMUX with two, three, and four input lines are proposed for the realization of QUOs belonging to the eight groups. A systematic procedure for the selection of QMUX and the implementation of the QUOs are given. The QMUXs are designed using CMOS ICs. The hardware required for their implementation is also discussed.

Analogue-to-quaternary converterst

This paper proposes two circuits for the realization of analogue-to-quaternary converters (AQCs) viz., pipeline AQC and circulation AQC. The proposed AQCs make use of three quaternary circuits namely four level comparator, multiplexer and D flip-flops. These circuits and also the relevant control circuits required in the realization of AQCs are described. A comparison of the two methods is made.

Serial quaternary-to-analogue converters

Circuits for realizing serial quaternary-to-analogue converters (QACs) are proposed in this paper. Three techniques are presented based on Shannon-Rack decoder, sample/hold serial digital-to-analogue converter and cyclic digital-to-analogue converter. Circuits for the generation of control signals and the multiplexer required in the realization of the QACs are also described. A comparison of the three methods is made.

Ternary function and circuit design using ternary multiplexers

The recent trend towards minimizing the interconnections in large scale integration (LSI) circuits has led to intensive investigation in the development of ternary circuits and the improvement of their design. The ternary multiplexer is a convenient and useful logic module which can be used as a basic building block in the design of a ternary system. This paper discusses a systematic procedure for the simplification and realization of ternary functions using ternary multiplexers as building blocks. Both single level and multilevel multiplexing techniques are considered. The importance of the design procedure is highlighted by considering two specific applications, namely, the development of ternary adder/subtractor and TCD to ternary converter.

A Study of Practical Biological Phantoms with Simple Instrumentation for Electrical Impedance Tomography (EIT)

16-electrode phantoms are developed and studied with a simple instrumentation developed for Electrical Impedance Tomography. An analog instrumentation is developed with a sinusoidal current generator and signal conditioner circuit. Current generator is developed withmodified Howland constant current source fed by a voltage controlled oscillator and the signal conditioner circuit consisting of an instrumentation amplifier and a narrow band pass filter. Electronic hardware is connected to the electrodes through a DIP switch based multiplexer module. Phantoms with different electrode size and position are developed and the EIT forward problem is studied using the forward solver. A low frequency low magnitude sinusoidal current is injected to the surface electrodes surrounding the phantom boundary and the differential potential is measured by a digital multimeter. Comparing measured potential with the simulated data it is intended to reduce the measurement error and an optimum phantom geometry is suggested. Result shows that the common mode electrode reduces the common mode error of the EIT electronics and reduces the error potential in the measured data. Differential potential is reduced up to 67 mV at the voltage electrode pair opposite to the current electrodes. Offset potential is measured and subtracted from the measured data for further correction. It is noticed that the potential data pattern depends on the electrode width and the optimum electrode width is suggested. It is also observed that measured potential becomes acceptable with a 20 mm solution column above and below the electrode array level.

Resistivity imaging of a reconfigurable phantom with circular inhomogeneities in 2D-electrical impedance tomography

Resistivity imaging of a reconfigurable phantom with circular inhomogeneities is studied with a simple instrumentation and data acquisition system for Electrical Impedance Tomography. The reconfigurable phantom is developed with stainless steel electrodes and a sinusoidal current of constant amplitude is injected to the phantom boundary using opposite current injection protocol. Nylon and polypropylene cylinders with different cross sectional areas are kept inside the phantom and the boundary potential data are collected. The instrumentation and the data acquisition system with a DIP switch-based multiplexer board are used to inject a constant current of desired amplitude and frequency. Voltage data for the first eight current patterns (128 voltage data) are found to be sufficient to reconstruct the inhomogeneities and hence the acquisition time is reduced. Resistivity images are reconstructed from the boundary data for different inhomogeneity positions using EIDORS-2D. The results show that the shape and resistivity of the inhomogeneity as well as the background resistivity are successfully reconstructed from the potential data for single or double inhomogeneity phantoms. The resistivity images obtained from the single and double inhomogeneity phantom clearly indicate the inhomogeneity as the high resistive material. Contrast to noise ratio (CNR) and contrast recovery (CR) of the reconstructed images are found high for the inhomogeneities near all the electrodes arbitrarily chosen for the entire study. (C) 2010 Elsevier Ltd. All rights reserved.

Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay

The use of delayed coefficient adaptation in the least mean square (LMS) algorithm has enabled the design of pipelined architectures for real-time transversal adaptive filtering. However, the convergence speed of this delayed LMS (DLMS) algorithm, when compared with that of the standard LMS algorithm, is degraded and worsens with increase in the adaptation delay. Existing pipelined DLMS architectures have large adaptation delay and hence degraded convergence speed. We in this paper, first present a pipelined DLMS architecture with minimal adaptation delay for any given sampling rate. The architecture is synthesized by using a number of function preserving transformations on the signal flow graph representation of the DLMS algorithm. With the use of carry-save arithmetic, the pipelined architecture can support high sampling rates, limited only by the delay of a full adder and a 2-to-1 multiplexer. In the second part of this paper, we extend the synthesis methodology described in the first part, to synthesize pipelined DLMS architectures whose power dissipation meets a specified budget. This low-power architecture exploits the parallelism in the DLMS algorithm to meet the required computational throughput. The architecture exhibits a novel tradeoff between algorithmic performance (convergence speed) and power dissipation. (C) 1999 Elsevier Science B.V. All rights resented.

Some aids in the design of microstrip components II: Nomograms

Nomograms have been developed for coupled microstrips. With the help of these, it is possible to design various microstrip components. The design of a multiplexer using the directional filter is described and experimental results are given. Nomograms relating the even and odd mode impedances of coupled microstrip lines to the width to height rate and spacing to height ratio have been developed using the relations formulated by Schwarzmann. A multiplexer using directional filters is designed to operate with three channels at frequencies of 3÷3, 3÷4 and 3÷5 GHz and bandwidths of 10 MHz in each channel. Experimental results are given. The design specifications are satisfied reasonably well.

Surface electrode switching of a 16-electrode wireless EIT system using RF-based digital data transmission scheme with 8 channel encoder/decoder ICs

A Radio Frequency (RF) based digital data transmission scheme with 8 channel encoder/decoder ICs is proposed for surface electrode switching of a 16-electrode wireless Electrical Impedance Tomography (EIT) system. A RF based wireless digital data transmission module (WDDTM) is developed and the electrode switching of a EIT system is studied by analyzing the boundary data collected and the resistivity images of practical phantoms. An analog multiplexers based electrode switching module (ESM) is developed with analog multiplexers and switched with parallel digital data transmitted by a wireless transmitter/receiver (T-x/R-x) module working with radio frequency technology. Parallel digital bits are generated using NI USB 6251 card working in LabVIEW platform and sent to transmission module to transmit the digital data to the receiver end. The transmitter/receiver module developed is properly interfaced with the personal computer (PC) and practical phantoms through the ESM and USB based DAQ system respectively. It is observed that the digital bits required for multiplexer operation are sequentially generated by the digital output (D/O) ports of the DAQ card. Parallel to serial and serial to parallel conversion of digital data are suitably done by encoder and decoder ICs. Wireless digital data transmission module successfully transmitted and received the parallel data required for switching the current and voltage electrodes wirelessly. 1 mA, 50 kHz sinusoidal constant current is injected at the phantom boundary using common ground current injection protocol and the boundary potentials developed at the voltage electrodes are measured. Resistivity images of the practical phantoms are reconstructed from boundary data using EIDORS. Boundary data and the resistivity images reconstructed from the surface potentials are studied to assess the wireless digital data transmission system. Boundary data profiles of the practical phantom with different configurations show that the multiplexers are operating in the required sequence for common ground current injection protocol. The voltage peaks obtained at the proper positions in the boundary data profiles proved the sequential operation of multiplexers and successful wireless transmission of digital bits. Reconstructed images and their image parameters proved that the boundary data are successfully acquired by the DAQ system which in turn again indicates a sequential and proper operation of multiplexers as well as the successful wireless transmission of digital bits. Hence the developed RF based wireless digital data transmission module (WDDTM) is found suitable for transmitting digital bits required for electrode switching in wireless EIT data acquisition system. (C) 2011 Elsevier Ltd. All rights reserved.

Open loop Model for WDM Links

Wavelength Division Multiplexing (WDM) techniques overfibrelinks helps to exploit the high bandwidth capacity of single mode fibres. A typical WDM link consisting of laser source, multiplexer/demultiplexer, amplifier and detectoris considered for obtaining the open loop gain model of the link. The methodology used here is to obtain individual component models using mathematical and different curve fitting techniques. These individual models are then combined to obtain the WDM link model. The objective is to deduce a single variable model for the WDM link in terms of input current to system. Thus it provides a black box solution for a link. The Root Mean Square Error (RMSE) associated with each of the approximated models is given for comparison. This will help the designer to select the suitable WDM link model during a complex link design.