Cell versus message level performances in ATM networks

The goal of this paper is to provide some insight into the relations that exist between cell level and message level performance guarantees in the context of ATM networks. Cell level guarantees are typically what the network is capable of providing, while message level guarantees are the ones of interest to users. It is, therefore, important to understand how the two are related, and which factors influence this relation. There are many different performance measures that are of importance, and in this paper we try to touch on the (three) most relevant ones. This includes comparing cell and message loss probabilities, average cell and message delays, and cell and message jitter. Specifically, we show that cell and message loss probabilities can exhibit significant differences, which strongly depend on traffic characteristics such as peak rate and burst size, i.e., for a fixed cell loss probability, the message loss probability can greatly vary when peak rate and burst size change. One reason for this sensitivity, is that message loss depends on what happen to all the cells in a message. For delay and jitter, we also find that peak rate and burst size play a role in determining the relation between cell and message performance. However, this sensitivity is not as acute as with losses since message delay and jitter are typically determined by the performance seen by only one cell, the last cell in a message. In the paper, we provide quantitative examples that illustrate the range of behaviors and identify the impact of different parameters.

Microcracking in concrete under repeated compressive loads

The nature of microcracks formed in concrete under repeated uniaxial compressive loads are investigated by experiments on prismatic specimens. The distribution and orientation of cracks formed are studied by optical microscopic techniques. The basic failure mechanism of concrete at the phenomenological and internal structural level are examined by the formation and propagation of cracks. The tests have indicated that local tensile failures constitute the dominant mode of fracture, with the bond cracks forming the major percentage of the total magnitude of cracks. Significant differences were observed in the proportion of bond cracks formed under static and repeated load systems.

Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique

The increasing variability in device leakage has made the design of keepers for wide OR structures a challenging task. The conventional feedback keepers (CONV) can no longer improve the performance of wide dynamic gates for the future technologies. In this paper, we propose an adaptive keeper technique called rate sensing keeper (RSK) that enables faster switching and tracks the variation across different process corners. It can switch upto 1.9x faster (for 20 legs) than CONV and can scale upto 32 legs as against 20 legs for CONV in a 130-nm 1.2-V process. The delay tracking is within 8% across the different process corners. We demonstrate the circuit operation of RSK using a 32 x 8 register file implemented in an industrial 130-nm 1.2-V CMOS process. The performance of individual dynamic logic gates are also evaluated on chip for various keeper techniques. We show that the RSK technique gives superior performance compared to the other alternatives such as Conditional Keeper (CKP) and current mirror-based keeper (LCR).

Improving fault detection and reliability in FDDI networks

FDDI (Fibre Distributed Data Interface) is a 100 Mbit/s token ring network with two counter rotating optical rings. In this paper various possible faults (like lost token, link failures, etc.) are considered, and fault detection and the ring recovery process in case of a failure and the reliability mechanisms provided are studied. We suggest a new method to improve the fault detection and ring recovery process. The performance improvement in terms of station queue length and the average delay is compared with the performance of the existing fault detection and ring recovery process through simulation. We also suggest a modification for the physical configuration of the FDDI networks within the guidelines set by the standard to make the network more reliable. It is shown that, unlike the existing FDDI network, full connectivity is maintained among the stations even when multiple single link failures occur. A distributed algorithm is proposed for link reconfiguration of the modified FDDI network when many successive as well as simultaneous link failures occur. The performance of the modified FDDI network under link failures is studied through simulation and compared with that of the existing FDDI network.

Generalized State Estimation and Model Predictive Guidance for Spiraling and Ballistic Targets

An extended Kalman filter based generalized state estimation approach is presented in this paper for accurately estimating the states of incoming high-speed targets such as ballistic missiles. A key advantage of this nine-state problem formulation is that it is very much generic and can capture spiraling as well as pure ballistic motion of targets without any change of the target model and the tuning parameters. A new nonlinear model predictive zero-effort-miss based guidance algorithm is also presented in this paper, in which both the zero-effort-miss as well as the time-to-go are predicted more accurately by first propagating the nonlinear target model (with estimated states) and zero-effort interceptor model simultaneously. This information is then used for computing the necessary lateral acceleration. Extensive six-degrees-of-freedom simulation experiments, which include noisy seeker measurements, a nonlinear dynamic inversion based autopilot for the interceptor along with appropriate actuator and sensor models and magnitude and rate saturation limits for the fin deflections, show that near-zero miss distance (i.e., hit-to-kill level performance) can be obtained when these two new techniques are applied together. Comparison studies with an augmented proportional navigation based guidance shows that the proposed model predictive guidance leads to a substantial amount of conservation in the control energy as well.

External support and innovation performance of SMEs in Bangalore: Role of firm level factors

This paper probes the role of internal factors in SMEs in obtaining external support and achieving innovation performance in the context of auto component, electronics and machine tool industries of Bangalore in India. Using step-wise logistic regression analysis, the study found that only if SMEs have internal technical competence in terms of technically qualified entrepreneur, an exclusive design centre, and innovate more frequently, they will be able to obtain external support. Further using step-wise multiple regression the study concluded that SMEs which have come up to implement innovative ideas or exploit market opportunities and which have obtained external support with technically qualified entrepreneurs are able to exhibit better innovation performance.

Effect of residual stresses and metallographic stability on the over all performance of integral diaphragm material

The integral diaphragm pressure transducer consists of a diaphragm machined from precipitation hardened martensitic (APX4) steel. Its performance is quite significant as it depends upon various factors such as mechanical properties including induced residual stress levels, metallurgical and physical parameters due to different stages of processing involved. Hence, the measurement and analysis of residual stress becomes very important from the point of in-service assessment of a component. In the present work, the stress measurements have been done using the X-ray diffraction (XRD) technique, which is a non-destructive test (NDT). This method is more reliable and widely used compared to the other NDT techniques. The metallurgical aspects have been studied by adopting the conventional metallographic practices including examination of microstructure using light microscope. The dimensional measurements have been carried out using dimensional gauge. The results of the present investigation reveals that the diaphragm material after undergoing series of realization processes has yielded good amount of retained austenite in it. Also, the presence of higher compressive stresses induced in the transducer results in non-linearity, zero shift and dimensional instability. The problem of higher retained austenite content and higher compressive stress have been overcome by adopting a new realization process involving machining and cold and hot stabilization soak which has brought down the retained austenite content to about 5–6% and acceptable level of compressive stress in the range −100 to −150 MPa with fine tempered martensitic phase structure and good dimensional stability. The new realization process seems to be quite effective in terms of controlling retained austenite content, residual stress, metallurgical phase as well as dimensional stability and this may result in minimum zero shift of the diaphragm system.

Studies on design, fabrication and reliability assessment of embedded passives on a high-density interconnect (HDI) organic substrate using a sequential build-up process

One of the foremost design considerations in microelectronics miniaturization is the use of embedded passives which provide practical solution. In a typical circuit, over 80 percent of the electronic components are passives such as resistors, inductors, and capacitors that could take up to almost 50 percent of the entire printed circuit board area. By integrating passive components within the substrate instead of being on the surface, embedded passives reduce the system real estate, eliminate the need for discrete and assembly, enhance electrical performance and reliability, and potentially reduce the overall cost. Moreover, it is lead free. Even with these advantages, embedded passive technology is at a relatively immature stage and more characterization and optimization are needed for practical applications leading to its commercialization.This paper presents an entire process from design and fabrication to electrical characterization and reliability test of embedded passives on multilayered microvia organic substrate. Two test vehicles focusing on resistors and capacitors have been designed and fabricated. Embedded capacitors in this study are made with polymer/ceramic nanocomposite (BaTiO3) material to take advantage of low processing temperature of polymers and relatively high dielectric constant of ceramics and the values of these capacitors range from 50 pF to 1.5 nF with capacitance per area of approximately 1.5 nF/cm(2). Limited high frequency measurement of these capacitors was performed. Furthermore, reliability assessments of thermal shock and temperature humidity tests based on JEDEC standards were carried out. Resistors used in this work have been of three types: 1) carbon ink based polymer thick film (PTF), 2) resistor foils with known sheet resistivities which are laminated to printed wiring board (PWB) during a sequential build-up (SBU) process and 3) thin-film resistor plating by electroless method. Realization of embedded resistors on conventional board-level high-loss epoxy (similar to 0.015 at 1 GHz) and proposed low-loss BCB dielectric (similar to 0.0008 at > 40 GHz) has been explored in this study. Ni-P and Ni-W-P alloys were plated using conventional electroless plating, and NiCr and NiCrAlSi foils were used for the foil transfer process. For the first time, Benzocyclobutene (BCB) has been proposed as a board level dielectric for advanced System-on-Package (SOP) module primarily due to its attractive low-loss (for RF application) and thin film (for high density wiring) properties.Although embedded passives are more reliable by eliminating solder joint interconnects, they also introduce other concerns such as cracks, delamination and component instability. More layers may be needed to accommodate the embedded passives, and various materials within the substrate may cause significant thermo -mechanical stress due to coefficient of thermal expansion (CTE) mismatch. In this work, numerical models of embedded capacitors have been developed to qualitatively examine the effects of process conditions and electrical performance due to thermo-mechanical deformations.Also, a prototype working product with the board level design including features of embedded resistors and capacitors are underway. Preliminary results of these are presented.

A New Liquid Level Sensor for Process-Control Applications

Many process-control systems are air-operated. In such an environment, it would be desirable and economical to use pneumatic sensors. Bubble-back pressure sensors perform quite satisfactorily, but in case of viscous inflammable and slurry-like liquids with a tendency to froth, this level sensor is inadequate. The method suggested in this paper utilizes a pneumatic capacitor, one boundary of which is formed by the liquid level, to modulate a fluid amplifier feedback oscillator. The absence of moving parts and economy obtained makes this method attractive for process-control applications. The system has been mathematically modeled and simulated on an IBM 360/44 digital computer. Experimental values compare fairly well with the theoretical results. For the range tested, the sensor is found to have a linear frequency variation with the liquid level Extended running in the laboratory shows that the system is very reliable. This system has been found insensitive to temperature variations of up to 15ðC.

Influence of subcontracting on innovation and economic performance of SMEs in Indian automobile industry

Trans-national corporations (TNCs) expanding their production bases to developing countries having better conditions of manufacturing and domestic markets provide increasing opportunities for local small and medium enterprises (SMEs) to have subcontracting relationships with these TNCs Even though some theoretical and a few empirical studies throw light on the nature of assistance provided by TNCs to local SMEs through subcontracting relationships none of the studies so far quantitatively analysed the role of this assistance on the innovative performance of SMEs leading to better economic performance This paper probes the extent and diversity of assistance received by SMEs from a TNC through subcontracting and its influence on technological innovations and economic performance of SMEs in the Indian automobile industry Indian SMEs were able to receive mainly product related and purchase process assistance thereby implying that subcontracting is largely confined to purchase-supply relationships However assistance received through subcontracting is beneficial as It promoted technological innovations of SMEs the higher the degree of assistance the higher the level of innovations carried out by these SMEs which in turn facilitated their economic performance Thus this paper substantiates in the Indian context that subcontracting relationship with a TNC can be an important source of technological innovations and enhanced economic performance for SMEs (C) 2010 Elsevier Ltd All rights reserved

Structured systems methodology for evaluation of random interruptions in continuous process type manufacturing systems

A structured systems methodology was developed to analyse the problems of production interruptions occurring at random intervals in continuous process type manufacturing systems. At a macro level the methodology focuses on identifying suitable investment policies to reduce interruptions of a total manufacturing system that is a combination of several process plants. An interruption-tree-based simulation model was developed for macroanalysis. At a micro level the methodology focuses on finding the effects of alternative configurations of individual process plants on the overall system performance. A Markov simulation model was developed for microlevel analysis. The methodology was tested with an industry-specific application.

Modeling of the Effects of Process Variations on Circuit Delay at 65nm

A novel methodology for modeling the effects of process variations on circuit delay performance is proposed by relating the variations in process parameters to variations in delay metric of a complex digital circuit. The delay of a 2-input NAND gate with 65nm gate length transistors is extensively characterized by mixed-mode simulations which is then used as a library element. The variation in saturation current Ionat the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. A 4-bit x 4-bit Wallace tree multiplier circuit is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, to obtain delay distributions, by an extensive Monte Carlo analysis. An analytical model based on CV/I metric is proposed, to extend this methodology for a generic technology library with a variety of library elements.

Performance analysis of subband-level channel quality indicator feedback scheme of LTE

Frequency-domain scheduling and rate adaptation enable next generation wireless cellular systems such as Long Term Evolution (LTE) to achieve significantly higher downlink throughput. LTE assigns subcarriers in chunks, called physical resource blocks (PRBs), to users to reduce control signaling overhead. To reduce the enormous feedback overhead, the channel quality indicator (CQI) report that is used to feed back channel state information is averaged over a subband, which, in turn, is a group of multiple PRBs. In this paper, we develop closed-form expressions for the throughput achieved by the subband-level CQI feedback mechanism of LTE. We show that the coarse frequency resolution of the CQI incurs a significant loss in throughput and limits the multi-user gains achievable by the system. We then show that the performance can be improved by means of an offset mechanism that effectively makes the users more conservative in reporting their CQI.

Space vector based bus clamped PWM algorithms for three level inverters: implementation, performance analysis and application considerations

This paper describes the different types of space vector based bus clamped PWM algorithms for three level inverters. A novel bus clamp PWM algorithm for low modulation indices region is also presented. The principles and switching sequences of all the types of bus clamped algorithms for high switching frequency are presented. Synchronized version of the PWM sequences for high power applications where switching frequency is low is also presented. The implementation details on DSP based digital controller and experimental results are presented. The THD of the output waveforms is studied for the entire operating region and is compared with the conventional space vector PWM technique. The bus clamped techniques can be used to reduce the switching losses or to improve the output voltage quality or both.. Different issues dominate depending on the type of application and power rating of the inverters. The results presented in this paper can be used for judicious use of the PWM techniques, which result in improved system efficiency and performance.