Delamination Tolerance in Composites under Fatigue Loading

Delamination is one of the most commonly occurring defects in laminated composite structures. Under operating fatigue loads on the laminate this delamination could grow and totally delaminate certain number of layers from the base laminate. This will result in loss of both compressive residual strength and buckling margins available. In this paper, geometrically non-linear analysis and evaluation of Strain Energy Release Rates using MVCCI technique is presented. The problems of multiple delamination, effect of temperature exposure and delamination from pin loaded holes are addressed. Numerical results are presented to draw certain inferences of importance to design of high technology composite structures such as aircraft wing.

Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well

Solar powered high voltage energization for vehicular exhaust cleaning: A step towards possible retrofitting in vehicles

This paper proposes a novel way of generating high voltage for electric discharge plasma in controlling NOx emission in diesel engine exhaust. A solar powered high frequency electric discharge topology has been suggested that will improve the size and specific energy density required when compared to the traditional repetitive pulse or 50 Hz AC energization. This methodology has been designed, fabricated and experimentally verified by conducting studies on real diesel engine exhaust.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have implemented a Firewall with this architecture in reconflgurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results in both speed and area improvement when it is implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields. High throughput classification invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly in terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for the worst case packet size. The Firewall rule update involves only memory re-initialization in software without any hardware change.

Crop Classification using Biologically-inspired Techniques with High Resolution Satellite Image

Remote sensing provides a lucid and effective means for crop coverage identification. Crop coverage identification is a very important technique, as it provides vital information on the type and extent of crop cultivated in a particular area. This information has immense potential in the planning for further cultivation activities and for optimal usage of the available fertile land. As the frontiers of space technology advance, the knowledge derived from the satellite data has also grown in sophistication. Further, image classification forms the core of the solution to the crop coverage identification problem. No single classifier can prove to satisfactorily classify all the basic crop cover mapping problems of a cultivated region. We present in this paper the experimental results of multiple classification techniques for the problem of crop cover mapping of a cultivated region. A detailed comparison of the algorithms inspired by social behaviour of insects and conventional statistical method for crop classification is presented in this paper. These include the Maximum Likelihood Classifier (MLC), Particle Swarm Optimisation (PSO) and Ant Colony Optimisation (ACO) techniques. The high resolution satellite image has been used for the experiments.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have Implemented a Firewall with this architecture in reconfigurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using, our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results In both speed and area Improvement when It is Implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields.High throughput classification Invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly In terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware Implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for file worst case packet size. The Firewall rule update Involves only memory re-initialiization in software without any hardware change.

Future switching technology: bacterial protein-based programmable all-optical switch for integrated optics applications?

We report on the bacterial protein-based all-optical switches which operate at low laser power, high speed and fulfil most of the requirements to be an ideal all-optical switch without any moving parts involved. This consists of conventional optical waveguides coated with bacteriorhodopsin films at switching locations. The principle of operation of the switch is based on the light-induced refractive index change of bacteriorhodopsin. This approach opens the possibility of realizing proteinbased all-optical switches for communication network, integrated optics and optical computers.

CFD analysis of high frequency miniature pulse tube refrigerators for space applications with thermal non-equilibrium model

High frequency, miniature, pulse tube cryocoolers are extensively used in space applications because of their simplicity. Parametric studies of inertance type pulse tube cooler are performed with different length-to-diameter ratios of the pulse tube with the help of the FLUENT (R) package. The local thermal non-equilibrium of the gas and the matrix is taken into account for the modeling of porous zones, in addition to the wall thickness of the components. Dynamic characteristics and the actual mechanism of energy transfer in pulse are examined with the help of the pulse tube wall time constant. The heat interaction between pulse tube wall and the oscillating gas, leading to surface heat pumping, is quantified. The axial heat conduction is found to reduce the performance of the pulse tube refrigerator. The thermal non-equilibrium predicts a higher cold heat exchanger temperature compared to thermal equilibrium. The pressure drop through the porous medium has a strong non-linear effect due to the dominating influence of Forchheimer term over that of the linear Darcy term at high operating frequencies. The phase angle relationships among the pressure, temperature and the mass flow rate in the porous zones are also important in determining the performance of pulse tuberefrigerator.

Gasifier stoves - science, technology and field outreach

Development of a new class of single pan high efficiency, low emission stoves, named gasifier stoves, that promise constant power that can be controlled using any solid biomass fuel in the form of pellets is reported here. These stoves use battery-run fan-based air supply for gasification (primary air) and for combustion (secondary air).Design with the correct secondary air flow ensures near-stoichiometric combustion that allows attainment of peak combustion temperatures with accompanying high water boiling efficiencies (up to 50% for vessels of practical relevance) and very low emissions (of carbon monoxide, particulate matter and oxides of nitrogen). The use of high density agro-residue based pellets or coconut shell pieces ensures operational duration of about an hour or more at power levels of 3 kWth (similar to 12 g/min). The principles involved and the optimization aspects of the design are outlined. The dependence of efficiency and emissions on the design parameters are described. The field imperatives that drive the choice of the rechargeable battery source and the fan are brought out. The implications of developments of Oorja-Plus and OorjaSuper stoves to the domestic cooking scenario of India are briefly discussed. The process development, testing and internal qualification tasks were undertaken by Indian Institute of Science. Product development and the fuel pellet production were dealt with by First Energy Private Ltd.Close interaction at several times during this period has helped progress the project from the laboratory to large scale commercial operation. At this time, over four hundred thousand stoves and 30 kilotonnes fuel have been sold in four states in India.

A novel fibre-coated sorbent for rapid removal of heavy metals from wastewater. Sorption of Zinc(II) from dilute aqueous solutions in the presence of high concentrations of common salts

The commercial acrylic fibre "Cashmilon" was partially hydrolyzed to convert a fraction of its nitrile (-CN) groups to carboxylic acid (-COOH) groups and then coated with polyethylenimine (PEI) resin and cross-linked with glutaraldehyde to produce a novel gel-coated fibrous sorbent with multiple functionalities of cationic, anionic and chelating types, and significantly faster sorption kinetics than bead-form sorbents. The sorption properties of the fibrous sorbent were measured using Zn(II) in aqueous solution as the sorbate to determine the effects of pH and the presence of common ions in the solution on the sorption capacity. The rate of sorption on the gel-coated fibre was measured in comparison with that on Amberlite IRA-68 weak-base resin beads, to demonstrate the marked difference between fibre and bead-form sorbents in their kinetic behaviour.

High-Throughput Flexible Constraint Length Viterbi Decoders on De Bruijn, Shuffle-Exchange and Butterfly Connected Architectures

Flexible constraint length channel decoders are required for software defined radios. This paper presents a novel scalable scheme for realizing flexible constraint length Viterbi decoders on a de Bruijn interconnection network. Architectures for flexible decoders using the flattened butterfly and shuffle-exchange networks are also described. It is shown that these networks provide favourable substrates for realizing flexible convolutional decoders. Synthesis results for the three networks are provided and a comparison is performed. An architecture based on a 2D-mesh, which is a topology having a nominally lesser silicon area requirement, is also considered as a fourth point for comparison. It is found that of all the networks considered, the de Bruijn network offers the best tradeoff in terms of area versus throughput.

A novel fibre-coated sorbent for rapid removal of heavy metals from wastewater. Sorption of Zinc(II) from dilute aqueous solutions in the presence of high concentrations of common salts

The commercial acrylic fibre "Cashmilon" was partially hydrolyzed to convert a fraction of its nitrile (-CN) groups to carboxylic acid (-COOH) groups and then coated with polyethylenimine (PEI) resin and cross-linked with glutaraldehyde to produce a novel gel-coated fibrous sorbent with multiple functionalities of cationic, anionic and chelating types, and significantly faster sorption kinetics than bead-form sorbents. The sorption properties of the fibrous sorbent were measured using Zn(II) in aqueous solution as the sorbate to determine the effects of pH and the presence of common ions in the solution on the sorption capacity. The rate of sorption on the gel-coated fibre was measured in comparison with that on Amberlite IRA-68 weak-base resin beads, to demonstrate the marked difference between fibre and bead-form sorbents in their kinetic behaviour.

High performance VLSI architecture design for H.264 CAVLC decoder

H.264 video standard achieves high quality video along with high data compression when compared to other existing video standards. H.264 uses context-based adaptive variable length coding (CAVLC) to code residual data in Baseline profile. In this paper we describe a novel architecture for CAVLC decoder including coeff-token decoder, level decoder total-zeros decoder and run-before decoder UMC library in 0.13 mu CMOS technology is used to synthesize the proposed design. The proposed design reduces chip area and improves critical path performance of CAVLC decoder in comparison with [1]. Macroblock level (including luma and chroma) pipeline processing for CAVLC is implemented with an average of 141 cycles (including pipeline buffering) per macroblock at 250MHz clock frequency. To compare our results with [1] clock frequency is constrained to 125MHz. The area required for the proposed architecture is 17586 gates, which is 22.1% improvement in comparison to [1]. We obtain a throughput of 1.73 * 10(6) macroblocks/second, which is 28% higher than that reported in [1]. The proposed design meets the processing requirement of 1080HD [5] video at 30frames/seconds.