Design and implementation of a PC-based FPGA tester

A new range of programmable logic devices are revolutionizing the way complex digital hardware is designed and built all over the world. Being able to test these devices in order to validate and dynamically improve on the design is crucial. This paper describes a low-cost FPGA tester that can test SRAM based FPGAs in the laboratory.

Sizable photocurrent and emission from solid state devices based on CdS nanoparticles

CdS nanoparticles exhibit size dependent optical and electrical properties. We report here the photocurrent and I-V characteristic studies of CdS nanoparticle devices. A sizable short circuit photocurrent was observed in the detection range governed by the size of the clusters. We speculate on the mechanisms leading to the photocurrent and emission in these nanometer scale systems.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have implemented a Firewall with this architecture in reconflgurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results in both speed and area improvement when it is implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields. High throughput classification invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly in terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for the worst case packet size. The Firewall rule update involves only memory re-initialization in software without any hardware change.

Programming an FPGA to Emulate the Dynamics of DC Machines

This paper presents the programming an FPGA (Field Programmable Gate Array) to emulate the dynamics of DC machines. FPGA allows high speed real time simulation with high precision. The described design includes block diagram representation of DC machine, which contain all arithmetic and logical operations. The real time simulation of the machine in FPGA is controlled by user interfaces they are Keypad interface, LCD display on-line and digital to analog converter. This approach provides emulation of electrical machine by changing the parameters. Separately Exited DC machine implemented and experimental results are presented.

FPGA based digital platform for the control of AC drives

This paper presents the new trend of FPGA (Field programmable Gate Array) based digital platform for the control of power electronic systems. There is a rising interest in using digital controllers in power electronic applications as they provide many advantages over their analog counterparts. A board comprising of Cyclone device EP1C12Q240C8 of Altera is used for developing this platform. The details of this board are presented. This developed platform can be used for the controller applications such as UPS, Induction Motor drives and front end converters. A real time simulation of a system can also be done. An open-loop induction motor drive has been implemented using this board and experimental results are presented.

Real-time simulation of electrical machines on FPGA platform

This paper presents real-time simulation models of electrical machines on FPGA platform. Implementation of the real-time numerical integration methods with digital logic elements is discussed. Several numerical integrations are presented. A real-time simulation of DC machine is carried out on this FPGA platform and important transient results are presented. These results are compared to simulation results obtained through a commercial off-line simulation software.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have Implemented a Firewall with this architecture in reconfigurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using, our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results In both speed and area Improvement when It is Implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields.High throughput classification Invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly In terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware Implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for file worst case packet size. The Firewall rule update Involves only memory re-initialiization in software without any hardware change.

Use of narrow-pore filters in He II transfer devices - new results

With the aim of finding simple methods for the fabrication of He II refilling devices, He II flow has been studied through filters made from various fine powders (oxides and metals, grain sizes in the range 0.05–2 μm) by compacting them under pressure. The results obtained for the different states of He II flow, especially in the “breakthrough” and “easy flow” range, are explained by the fountain effect, He II hydrodynamics and the choking effect. According to the results, pressedpowder filters can be classified into three groups with different flow characteristics, of which the “good transfer filters” with a behaviour neatly described by simple theory are suitable for use in He II refilling devices.

Resistance Noise in Graphene Based Field Effect Devices

We present a low-frequency electrical noise measurement in graphene based field effect transistors. For single layer graphene (SLG), the resistance fluctuations is governed by the screening of the charge impurities by the mobile charges. However, in case of Bilayer graphene (BLG), the electrical noise is strongly connected to its band structure, and unlike single layer graphene, displays a minimum when the gap between the conduction and valence band is zero. Using double gated BLG devices we have tuned the zero gap and charge neutrality points independently, which offers a versatile mechanism to investigate the low-energy band structure, charge localization and screening properties of bilayer graphene

Oxides supported carbon air-electrodes for alkaline solution power devices

Porous carbon oxygen-reducing electrodes incorporated with perovskite oxide catalysts are reported. It has been possible to fabricate high-performance oxygen-reducing electrodes by introducing La0.5Sr0.5CoO3 and La0.99Sr0.01NiO3 with the activated coconut-shell charcoal; these electrodes could sustain load currents as high as 1 A cm−2 without serious degradation. A model to explain oxygen-reducing activity of these oxides has been proposed.

Proportional Weirs as Velocity Controlling Devices

Of the many factors that govern the settling phenomenon, the flow velocity in the settling tanks can be controlled favorably by fixing suitably designed weirs at the outlets of the tanks. The velocity at the bottom should not dislodge the particles that have already settled. These requirements might be met with by velocities which are controlled to be constant with respect to the depth of flow, or velocities which reduce linearly with increasing depth or velocities that vary inversely with the depth. To achieve these types of velocity control, new proportional weirs have been designed. Very near to the outlet of the tank, over a small length, the flow was found to be turbulent and noncompliant with the expected type of velocity control. This small length of the disturbance may be provided over and above the theoretical settling length of the tank, for efficient sedimentation.

Redefine: Runtime Reconfigurable Polymorphic ASIC

Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically interoperate between different standards and their derivatives. In order to achieve high resource utilization and low power dissipation, we propose REDEFINE, a polymorphic ASIC in which specialized hardware units are replaced with basic hardware units that can create the same functionality by runtime re-composition. It is a ``future-proof'' custom hardware solution for multiple applications and their derivatives in a domain. In this article, we describe a compiler framework and supporting hardware comprising compute, storage, and communication resources. Applications described in high-level language (e.g., C) are compiled into application substructures. For each application substructure, a set of compute elements on the hardware are interconnected during runtime to form a pattern that closely matches the communication pattern of that particular application. The advantage is that the bounded CEs are neither processor cores nor logic elements as in FPGAs. Hence, REDEFINE offers the power and performance advantage of an ASIC and the hardware reconfigurability and programmability of that of an FPGA/instruction set processor. In addition, the hardware supports custom instruction pipelining. Existing instruction-set extensible processors determine a sequence of instructions that repeatedly occur within the application to create custom instructions at design time to speed up the execution of this sequence. We extend this scheme further, where a kernel is compiled into custom instructions that bear strong producer-consumer relationship (and not limited to frequently occurring sequences of instructions). Custom instructions, realized as hardware compositions effected at runtime, allow several instances of the same to be active in parallel. A key distinguishing factor in majority of the emerging embedded applications is stream processing. To reduce the overheads of data transfer between custom instructions, direct communication paths are employed among custom instructions. In this article, we present the overview of the hardware-aware compiler framework, which determines the NoC-aware schedule of transports of the data exchanged between the custom instructions on the interconnect. The results for the FFT kernel indicate a 25% reduction in the number of loads/stores, and throughput improves by log(n) for n-point FFT when compared to sequential implementation. Overall, REDEFINE offers flexibility and a runtime reconfigurability at the expense of 1.16x in power and 8x in area when compared to an ASIC. REDEFINE implementation consumes 0.1x the power of an FPGA implementation. In addition, the configuration overhead of the FPGA implementation is 1,000x more than that of REDEFINE.

RF Sputtered Er2O3 Thin Films as High-k Gate Dielectrics for Germanium MOS Devices

We report the material and electrical properties of Erbium Oxide (Er2O3) thin films grown on n-Ge (100) by RF sputtering. The properties of the films are correlated with the processing conditions. The structural characterization reveals that the films annealed at 550 degrees C, has densified as compared to the as-grown ones. Fixed oxide charges and interface charges, both of the order of 10(13)/cm(2) is observed.

Dynamics and control of buckling type devices using SMA wire integrated beam

An analysis and design study using Shape Memory Alloy (SMA) wire integrated beam and its buckling shape control are reported. The dynamical system performance is analyzed with a mathematical set-up involving nonlocal and rate sensitive kinetics of phase transformation in the SMA wire. A standard phenomenological constitutive model reported by Brinson (1993) is modified by considering certain consistency conditions in the material property tensors and by eliminating spurious singularity. Considering the inhomogeneity effects, a finite element model of the SMA wire is developed. Simulations are carried out to study the buckling shape control of a beam integrated with SMA wire.

Space-charge limited conduction in doped polypyrrole devices

Doping dependent current-voltage (I-V) and capacitance-voltage (C-V) measurements were carried out on polypyrrole devices in metal-polymer-metal sandwich structure. Temperature dependent I-V measurements infer that space-charge limited conduction (SCLC) with exponential trap distribution is appropriate for the moderately doped samples, whereas trap-free SCLC is observed in lightly doped samples. Trap densities and energies are estimated, the effective mobility is calculated using the Poole-Frenkel model, and the mobility exhibits thermally activated behavior. Frequency dependent capacitance-voltage characteristics show a peak near zero bias voltage, which implies that these devices are symmetric with a negligible barrier height at the metal-polymer interface. Low frequency capacitance measurements have revealed a negative capacitance at higher voltages due to the processes associated with the injection and redistribution of space-charges. (C) 2010 American Institute of Physics.