A high performance scheme for EEG compression using a multichannel model

The amount of data contained in electroencephalogram (EEG) recordings is quite massive and this places constraints on bandwidth and storage. The requirement of online transmission of data needs a scheme that allows higher performance with lower computation. Single channel algorithms, when applied on multichannel EEG data fail to meet this requirement. While there have been many methods proposed for multichannel ECG compression, not much work appears to have been done in the area of multichannel EEG. compression. In this paper, we present an EEG compression algorithm based on a multichannel model, which gives higher performance compared to other algorithms. Simulations have been performed on both normal and pathological EEG data and it is observed that a high compression ratio with very large SNR is obtained in both cases. The reconstructed signals are found to match the original signals very closely, thus confirming that diagnostic information is being preserved during transmission.

Compiler-Directed Dynamic Voltage Scaling using Program Phases

Energy consumption has become a major constraint in providing increased functionality for devices with small form factors. Dynamic voltage and frequency scaling has been identified as an effective approach for reducing the energy consumption of embedded systems. Earlier works on dynamic voltage scaling focused mainly on performing voltage scaling when the CPU is waiting for memory subsystem or concentrated chiefly on loop nests and/or subroutine calls having sufficient number of dynamic instructions. This paper concentrates on coarser program regions and for the first time uses program phase behavior for performing dynamic voltage scaling. Program phases are annotated at compile time with mode switch instructions. Further, we relate the Dynamic Voltage Scaling Problem to the Multiple Choice Knapsack Problem, and use well known heuristics to solve it efficiently. Also, we develop a simple integer linear program formulation for this problem. Experimental evaluation on a set of media applications reveal that our heuristic method obtains a 38% reduction in energy consumption on an average, with a performance degradation of 1% and upto 45% reduction in energy with a performance degradation of 5%. Further, the energy consumed by the heuristic solution is within 1% of the optimal solution obtained from the ILP approach.

Model-following Neuro-adaptive approach for robust control of high performance aircrafts

Based on dynamic inversion, a relatively straightforward approach is presented in this paper for nonlinear flight control design of high performance aircrafts, which does not require the normal and lateral acceleration commands to be first transferred to body rates before computing the required control inputs. This leads to substantial improvement of the tracking response. Promising results are obtained from six degree-offreedom simulation studies of F-16 aircraft, which are found to be superior as compared to an existing approach (which is also based on dynamic inversion). The new approach has two potential benefits, namely reduced oscillatory response (including elimination of non-minimum phase behavior) and reduced control magnitude. Next, a model-following neuron-adaptive design is augmented the nominal design in order to assure robust performance in the presence of parameter inaccuracies in the model. Note that in the approach the model update takes place adaptively online and hence it is philosophically similar to indirect adaptive control. However, unlike a typical indirect adaptive control approach, there is no need to update the individual parameters explicitly. Instead the inaccuracy in the system output dynamics is captured directly and then used in modifying the control. This leads to faster adaptation, which helps in stabilizing the unstable plant quicker. The robustness study from a large number of simulations shows that the adaptive design has good amount of robustness with respect to the expected parameter inaccuracies in the model.

The poly dA helix: a new structural motif for high performance DNA-based molecular switches

We report a pH-dependent conformational transition in short, defined homopolymeric deoxyadenosines (dA(15)) from a single helical structure with stacked nucleobases at neutral pH to a double-helical, parallel-stranded duplex held together by AH-HA base pairs at acidic pH. Using native PAGE, 2D NMR, circular dichroism (CD) and fluorescence spectroscopy, we have characterized the two different pH dependent forms of dA(15). The pH-triggered transition between the two defined helical forms of dA(15) is characterized by CD and fluorescence. The kinetics of this conformational switch is found to occur on a millisecond time scale. This robust, highly reversible, pH-induced transition between the two well-defined structured states of dA(15)represents a new molecular building block for the construction of quick-response, pH-switchable architectures in structural DNA nanotechnology.

Use of a volatile buffer at ambient temperature *1: Versatile approach to the purification of self-complementary synthetic deoxyoligonucleotides by reversed-phase high-performance liquid chromatography

Abstract is not available.

HFinFET: A Scalable, High Performance, Low Leakage Hybrid n-Channel FET

In this letter, we propose the design and simulation study of a novel transistor, called HFinFET, which is a hybrid of an HEMT and a FinFET, to obtain excellent performance and good OFF-state control. Followed by the description of the design, 3-D device simulation has been performed to predict the characteristics of the device. The device has been benchmarked against published state of the art HEMT as well as planar and nonplanar Si n-MOSFET data of comparable gate length using standard benchmarking techniques.

High performance VLSI architecture design for H.264 CAVLC decoder

H.264 video standard achieves high quality video along with high data compression when compared to other existing video standards. H.264 uses context-based adaptive variable length coding (CAVLC) to code residual data in Baseline profile. In this paper we describe a novel architecture for CAVLC decoder including coeff-token decoder, level decoder total-zeros decoder and run-before decoder UMC library in 0.13 mu CMOS technology is used to synthesize the proposed design. The proposed design reduces chip area and improves critical path performance of CAVLC decoder in comparison with [1]. Macroblock level (including luma and chroma) pipeline processing for CAVLC is implemented with an average of 141 cycles (including pipeline buffering) per macroblock at 250MHz clock frequency. To compare our results with [1] clock frequency is constrained to 125MHz. The area required for the proposed architecture is 17586 gates, which is 22.1% improvement in comparison to [1]. We obtain a throughput of 1.73 * 10(6) macroblocks/second, which is 28% higher than that reported in [1]. The proposed design meets the processing requirement of 1080HD [5] video at 30frames/seconds.

Exploring energy-performance trade-offs for heterogeneous interconnect clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving clock speed, reducing energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires which leads to delay in execution and significantly high energy consumption.In this paper, we propose a new instruction scheduling algorithm that exploits scheduling slacks of instructions and communication slacks of data values together to achieve better energy-performance trade-offs for clustered architectures with heterogeneous interconnect. Our instruction scheduling algorithm achieves 35% and 40% reduction in communication energy, whereas the overall energy-delay product improves by 4.5% and 6.5% respectively for 2 cluster and 4 cluster machines with marginal increase (1.6% and 1.1%) in execution time. Our test bed uses the Trimaran compiler infrastructure.

Sensitive high-resolution ion microprobe U-Pb dating of prograde and retrograde ultrahigh-temperature metamorphism as exemplified by Sri Lankan granulites

Ultrahigh-temperature (UHT) granulites of the central Highland Complex, Sri Lanka, underwent some of the highest known peak temperatures of crustal metamorphism. Zircon and monazite U-Pb systems in granulites near Kandy, the highest grade region (similar to 1050 degrees C; 0.9 GPa), preserve both a record of the timing of prograde and retrograde phases of UHT metamorphism and evidence for the ages of older protolith components. Zircon grains from a quartz-saturated granulite containing relics of the peak UHT assemblage have remnant detrital cores with dates of ca. 2.5-0.83 Ga. Date clusters of ca. 1.7 and 1.04-0.83 Ga record episodes of zircon growth in the source region of the protolith sediment. Two generations of overgrowths with contrasting Th/U record metamorphic zircon growth at 569 +/- 5 and 551 +/- 7 Ma, probably in the absence and presence of monazite, respectively. The age of coexisting metamorphic monazite (547 +/- 7 Ma) is indistinguishable from that of the younger, low-Th/U zircon overgrowths. Zircon from a quartz-undersaturated monazite-absent UHT granulite with a mainly retrograde assemblage is mostly metamorphic (551 +/- 5 Ma). The ca. 570 Ma zircon overgrowths in the quartz-saturated granulite probably record partial melting just before or at the metamorphic peak. The ca. 550 Ma zircon in both rocks, and the ca. 550 Ma monazite in the quartz-saturated sample, record post-peak isothermal decompression. A possible model for this pressure-temperature-time evolution is ultrahot collisional orogeny during the assembly of Gondwana, locally superheated by basaltic underplating, followed by fast extensional exhumation.

Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well

Fabrication and evaluation of 450 F electrochemical redox supercapacitors using inexpensive and high-performance, polyaniline coated, stainless-steel electrodes

Redox supercapacitors using polyaniline (PANI) coated. stainless-steel (SS) electrodes have been assembled and characterized. PANI has been deposited on SS substrate by a potentiodynamic method from an acidic electrolyte which contains aniline monomer. By employing stacks of electrodes, each with a geometrical area of 24 cm(2), in acidic perchlorate electrolyte, a capacitance value of about 450 F has been obtained over a long cycle-life. Characterization studies have been carried out by galvanostatic charge-discharge cycling of the capacitors singly, as well as in series and parallel configurations. Various electrical parameters have been evaluated. Use of the capacitors in parallel with a battery for pulse-power loads. and also working of a toy fan connected to the charged capacitors have been demonstrated. A specific capacitance value of about 1300 F g(-1) of PANI has been obtained at a discharge power of about 0.5 kW kg(-1). This value is several times higher than those reported in the literature for PANI and is, perhaps, the highest value known for a capacitor material. The inexpensive SS substrate and the high-capacitance PANI are favorable factors for commercial exploitation. (C) 2002 Elsevier Science B.V. All rights reserved.

Potentiodynamically deposited polyaniline on stainless steel - Inexpensive, high-performance electrodes for electrochemical supercapacitors

Polyaniline (PANI) has been studied as an active material for electrochemical capacitors. Polymerization of aniline to PANI has been carried out potentiodynamically on a stainless steel (SS) substrate, instead of Pt-based substrates generally employed for this application. The PANI/SS electrodes have been evaluated by assembling symmetrical capacitors in NaClO(4) + HClO(4) mixed electrolyte and subjecting them to galvanostatic charge/discharge cycles between 0 and 0.75 V. The effect of substrate has been assessed by comparing the capacitance of PANI/SS and PANI/Pt electrodes. The capacitance of PANI/SS electrode is higher than that of PANI/Pt electrode by several times. The effect of sweep rate of potentiodynamic deposition of PANI/SS on capacitance has been investigated. At a power density of 0.5 kW kg(-1), a capacitance value of 815 F g(-1) of PANI is obtained for the deposition sweep rate of 200 mV s(-1). Increase in thickness of PANI on the SS substrate results in an increase in capacitance of PANI. This value of capacitance is the highest ever reported for any electrochemical capacitor material. Thus, in addition to a favorable economic aspect involved in using SS instead of Pt or Pt-based substrate, the advantage of higher capacitance of PANI has also been achieved. (C) 2002 The Electrochemical Society.

Improving Performance of Result Caches in Network Processors

Digest caches have been proposed as an effective method tospeed up packet classification in network processors. In this paper, weshow that the presence of a large number of small flows and a few largeflows in the Internet has an adverse impact on the performance of thesedigest caches. In the Internet, a few large flows transfer a majority ofthe packets whereas the contribution of several small flows to the totalnumber of packets transferred is small. In such a scenario, the LRUcache replacement policy, which gives maximum priority to the mostrecently accessed digest, tends to evict digests belonging to the few largeflows. We propose a new cache management algorithm called SaturatingPriority (SP) which aims at improving the performance of digest cachesin network processors by exploiting the disparity between the number offlows and the number of packets transferred. Our experimental resultsdemonstrate that SP performs better than the widely used LRU cachereplacement policy in size constrained caches. Further, we characterizethe misses experienced by flow identifiers in digest caches.

A Neuro-Adaptive Approach for Robust Control of High Performance Aircrafts with Parameter Inaccuracies

For high performance aircrafts, the flight control system needs to be quite effective in both assuring accurate tracking of pilot commands, while simultaneously assuring overall stability of the aircraft. In addition, the control system must also be sufficiently robust to cater to possible parameter variations. The primary aim of this paper is to enhance the robustness of the controller for a HPA using neuro-adaptive control design. Here the architecture employs a network of Gaussian Radial basis functions to adaptively compensate for the ignored system dynamics. A stable weight mechanism is determined using Lyapunov theory. The network construction and performance of the resulting controller are illustrated through simulations with a low-fidelity six –DOF model of F16 that is available in open literature.