An accurate method for the experimental evaluation of the acoustical impedance of a black box

Among different methods, the transmission-line or the impedance tube method has been most popular for the experimental evaluation of the acoustical impedance of any termination. The current state of method involves extrapolation of the measured data to the reflecting surface or exact locations of the pressure maxima, both of which are known to be rather tricky. The present paper discusses a method which makes use of the positions of the pressure minima and the values of the standing-wave ratio at these points. Lippert's concept of enveloping curves has been extended. The use of Smith or Beranek charts, with their inherent inaccuracy, has been altogether avoided. The existing formulas for the impedance have been corrected. Incidentally, certain other errors in the current literature have also been brought to light.Subject Classification: 85.20.

A method for the experimental evaluation of the acoustic characteristics of an engine exhaust system in the presence of mean flow

The paper deals with an exact analysis of standing waves in an impedance tube with mean flow. A method is offered for the experimental evaluation of the various wave parameters. Navier–Stokes equations have been solved for evaluating the volume velocity taking into account mean flow, viscosity, etc. The engine exhaust system has been characterized as an acoustic source with an acoustic pressure and internal impedance. A method is suggested for the evaluation of these hypothetical parameters using the exhaust pipe as an impedance tube.Subject Classification: [43]85.20; [43]20.40.

Experimental evaluation of the aeroacoustic characteristics of a source of pulsating gas flow

Amongv arioums ethodtsh,e t ransmissliionne o r thei mpedantcueb em ethohda sb eenm ospt opulafro r thee xperimenetavla luatioonf thea cousticiaml pedanocef a terminatioTnh. ee xistinmg ethodisn,c luding theo nesre porteeda rlierb, y thea uthorrse quirleo catioonf thes oundp ressumrei nima nd/orm axima, or elsem akeu se0 f somei terativep rocedureTsh. e presenpt aperd ealsw ith a methodo f analysios f standinwga vews hichd oesn otd epenodn anyo f thesein volvepdr ocedureIts i.s applicabtloe thec aseo f stationarays w ella sm ovingm ediaI.t enableosn to evaluatteh e impedancoef anyp assivbel ackb ox,a s well as the aeroacoustcich aracteristicosf a sourceo f pulsatingg asf low, with the leaste xperimentawl ork andc omputatiotinm ea ndw itht hee xtraa dvantagoef usinga givenim pedanctueb ef or wavelengtahss largea s fourt imesit s lengthA. methodo f externaml easuremenntost, involvinugs eo f anyi mpedance tubef, or evaluatintgh ea eroacouscthica racteristoicf as sourcoef pulsatingga sf lowi s alsod ealtw ith, based on the definition of attenuation or insertion loss of a muffler.

Theoretical and Experimental Evaluation of Pulsating Torque Produced by Induction Motor Drives Controlled With Advanced Bus-Clamping Pulsewidth Modulation

This paper investigates possible reduction of pulsating torque in open-loop and vector-controlled induction motor drives through deployment of certain advanced bus-clamping pulsewidth modulation (ABCPWM) method. Toward this goal, a simple and machine-independent method is proposed to analyze the torque harmonic spectrum of a voltage source inverter fed induction motor, operated with any real-time pulsewidth modulation (PWM) method. The analytically evaluated torque harmonic spectra, pertaining to conventional space vector PWM (CSVPWM), bus-clamping PWM (BCPWM), and ABCPWM, are validated through simulation and experimental results. Theoretical and experimental studies bring out the superiority of the ABCPWM in terms of torque harmonics over CSVPWM and BCPWM. The magnitude of the dominant torque harmonic with the ABCPWM scheme is shown to be significantly lower than that with CSVPWM, over a wide range of speed. The rms torque ripple (i.e., total rms value of all harmonic torques) is lower with ABCPWM than with BCPWM over the entire range of speed.

Measurement of the acoustical impedance of a black box at low frequencies using a shorter impedance tube

For the experimental evaluation of the acoustical impedance of a termination by the impedance-tube method at low frequencies, the length of the impedance tube is a problem. In the present paper, the method of exact analysis of standing waves developed by the authors for the stationary medium as well as for mean flow, has been extended for measurement of the acoustical impedance of a termination at low frequencies. The values of the tube attenuation factor and the wave number at the low frequency of interest are established from the experiment conducted, with the given impedance tube, at a higher frequency. Then, exciting the tube at the desired low frequency it is sufficient to measure sound pressure at three differenct locations (not necessarily the minima) in order to evaluate reflection coefficient and hence the impedance of the termination at that frequency.

Robust heuristics for scalable optimization of complex SQL queries

Modern database systems incorporate a query optimizer to identify the most efficient "query execution plan" for executing the declarative SQL queries submitted by users. A dynamic-programming-based approach is used to exhaustively enumerate the combinatorially large search space of plan alternatives and, using a cost model, to identify the optimal choice. While dynamic programming (DP) works very well for moderately complex queries with up to around a dozen base relations, it usually fails to scale beyond this stage due to its inherent exponential space and time complexity. Therefore, DP becomes practically infeasible for complex queries with a large number of base relations, such as those found in current decision-support and enterprise management applications. To address the above problem, a variety of approaches have been proposed in the literature. Some completely jettison the DP approach and resort to alternative techniques such as randomized algorithms, whereas others have retained DP by using heuristics to prune the search space to computationally manageable levels. In the latter class, a well-known strategy is "iterative dynamic programming" (IDP) wherein DP is employed bottom-up until it hits its feasibility limit, and then iteratively restarted with a significantly reduced subset of the execution plans currently under consideration. The experimental evaluation of IDP indicated that by appropriate choice of algorithmic parameters, it was possible to almost always obtain "good" (within a factor of twice of the optimal) plans, and in the few remaining cases, mostly "acceptable" (within an order of magnitude of the optimal) plans, and rarely, a "bad" plan. While IDP is certainly an innovative and powerful approach, we have found that there are a variety of common query frameworks wherein it can fail to consistently produce good plans, let alone the optimal choice. This is especially so when star or clique components are present, increasing the complexity of th- e join graphs. Worse, this shortcoming is exacerbated when the number of relations participating in the query is scaled upwards.

A mixed-split scheme for 2-D DPCM based LSF quantization

In this paper a mixed-split scheme is proposed in the context of 2-D DPCM based LSF quantization scheme employing split vector product VQ mechanism. Experimental evaluation shows that the new scheme is successfully being able to show better distortion performance than existing safety-net scheme for noisy channel even at considerably lower search complexity, by efficiently exploiting LSF trajectory behavior across the consecutive speech frames.

Points-to Analysis as a System of Linear Equations

We propose a novel formulation of the points-to analysis as a system of linear equations. With this, the efficiency of the points-to analysis can be significantly improved by leveraging the advances in solution procedures for solving the systems of linear equations. However, such a formulation is non-trivial and becomes challenging due to various facts, namely, multiple pointer indirections, address-of operators and multiple assignments to the same variable. Further, the problem is exacerbated by the need to keep the transformed equations linear. Despite this, we successfully model all the pointer operations. We propose a novel inclusion-based context-sensitive points-to analysis algorithm based on prime factorization, which can model all the pointer operations. Experimental evaluation on SPEC 2000 benchmarks and two large open source programs reveals that our approach is competitive to the state-of-the-art algorithms. With an average memory requirement of mere 21MB, our context-sensitive points-to analysis algorithm analyzes each benchmark in 55 seconds on an average.

Automatic Compilation of MATLAB Programs for Synergistic Execution on Heterogeneous Processors

MATLAB is an array language, initially popular for rapid prototyping, but is now being increasingly used to develop production code for numerical and scientific applications. Typical MATLAB programs have abundant data parallelism. These programs also have control flow dominated scalar regions that have an impact on the program's execution time. Today's computer systems have tremendous computing power in the form of traditional CPU cores and throughput oriented accelerators such as graphics processing units(GPUs). Thus, an approach that maps the control flow dominated regions to the CPU and the data parallel regions to the GPU can significantly improve program performance. In this paper, we present the design and implementation of MEGHA, a compiler that automatically compiles MATLAB programs to enable synergistic execution on heterogeneous processors. Our solution is fully automated and does not require programmer input for identifying data parallel regions. We propose a set of compiler optimizations tailored for MATLAB. Our compiler identifies data parallel regions of the program and composes them into kernels. The problem of combining statements into kernels is formulated as a constrained graph clustering problem. Heuristics are presented to map identified kernels to either the CPU or GPU so that kernel execution on the CPU and the GPU happens synergistically and the amount of data transfer needed is minimized. In order to ensure required data movement for dependencies across basic blocks, we propose a data flow analysis and edge splitting strategy. Thus our compiler automatically handles composition of kernels, mapping of kernels to CPU and GPU, scheduling and insertion of required data transfer. The proposed compiler was implemented and experimental evaluation using a set of MATLAB benchmarks shows that our approach achieves a geometric mean speedup of 19.8X for data parallel benchmarks over native execution of MATLAB.

Scalable Context-Sensitive Points-To Analysis Using Multi-Dimensional Bloom Filters

Context-sensitive points-to analysis is critical for several program optimizations. However, as the number of contexts grows exponentially, storage requirements for the analysis increase tremendously for large programs, making the analysis non-scalable. We propose a scalable flow-insensitive context-sensitive inclusion-based points-to analysis that uses a specially designed multi-dimensional bloom filter to store the points-to information. Two key observations motivate our proposal: (i) points-to information (between pointer-object and between pointer-pointer) is sparse, and (ii) moving from an exact to an approximate representation of points-to information only leads to reduced precision without affecting correctness of the (may-points-to) analysis. By using an approximate representation a multi-dimensional bloom filter can significantly reduce the memory requirements with a probabilistic bound on loss in precision. Experimental evaluation on SPEC 2000 benchmarks and two large open source programs reveals that with an average storage requirement of 4MB, our approach achieves almost the same precision (98.6%) as the exact implementation. By increasing the average memory to 27MB, it achieves precision upto 99.7% for these benchmarks. Using Mod/Ref analysis as the client, we find that the client analysis is not affected that often even when there is some loss of precision in the points-to representation. We find that the NoModRef percentage is within 2% of the exact analysis while requiring 4MB (maximum 15MB) memory and less than 4 minutes on average for the points-to analysis. Another major advantage of our technique is that it allows to trade off precision for memory usage of the analysis.

Compiler-Directed Dynamic Voltage Scaling using Program Phases

Energy consumption has become a major constraint in providing increased functionality for devices with small form factors. Dynamic voltage and frequency scaling has been identified as an effective approach for reducing the energy consumption of embedded systems. Earlier works on dynamic voltage scaling focused mainly on performing voltage scaling when the CPU is waiting for memory subsystem or concentrated chiefly on loop nests and/or subroutine calls having sufficient number of dynamic instructions. This paper concentrates on coarser program regions and for the first time uses program phase behavior for performing dynamic voltage scaling. Program phases are annotated at compile time with mode switch instructions. Further, we relate the Dynamic Voltage Scaling Problem to the Multiple Choice Knapsack Problem, and use well known heuristics to solve it efficiently. Also, we develop a simple integer linear program formulation for this problem. Experimental evaluation on a set of media applications reveal that our heuristic method obtains a 38% reduction in energy consumption on an average, with a performance degradation of 1% and upto 45% reduction in energy with a performance degradation of 5%. Further, the energy consumed by the heuristic solution is within 1% of the optimal solution obtained from the ILP approach.

An Empirical Analysis of Heterogeneity in IEEE 802.11 MAC Protocol Implementations and its Implications

Wireless LAN (WLAN) market consists of IEEE 802.11 MAC standard conformant devices (e.g., access points (APs), client adapters) from multiple vendors. Certain third party certifications such as those specified by the Wi-Fi alliance have been widely used by vendors to ensure basic conformance to the 802.11 standard, thus leading to the expectation that the available devices exhibit identical MAC level behavior. In this paper, however, we present what we believe to be the first ever set of experimental results that highlight the fact that WLAN devices from different vendors in the market can have heterogeneous MAC level behavior. Specifically, we demonstrate with examples and data that in certain cases, devices may not be conformant with the 802.11 standard while in other cases, they may differ in significant details that are not a part of mandatory specifications of the standard. We argue that heterogeneous MAC implementations can adversely impact WLAN operations leading to unfair bandwidth allocation, potential break-down of related MAC functionality and difficulties in provisioning the capacity of a WLAN. However, on the positive side, MAC level heterogeneity can be useful in applications such as vendor/model level device fingerprinting.

Specification Based Regression Testing Using Explicit State Space Enumeration

This paper presents a method of partial automation of specification based regression testing, which we call ESSE (Explicit State Space Enumeration). The first step in ESSE method is the extraction of a finite state model of the system making use of an already tested version of the system under test (SUT). Thereafter, the finite state model thus obtained is used to compute good test sequences that can be used to regression test subsequent versions of the system. We present two new algorithms for test sequence computation - both based on our finite state model generated by the above method. We also provide the details and results of the experimental evaluation of ESSE method. Comparison with a practically used random-testing algorithm has shown substantial improvements.

Compiler-assisted energy optimization for clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving the clock speed, reducing the energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires having high load capacitance which leads to delay in execution and significantly high energy consumption. Inter-cluster communication also introduces many short idle cycles, thereby significantly increasing the overall leakage energy consumption in the functional units. The trend towards miniaturization of devices (and associated reduction in threshold voltage) makes energy consumption in interconnects and functional units even worse, and limits the usability of clustered architectures in smaller technologies. However, technological advancements now permit the design of interconnects and functional units with varying performance and power modes. In this paper, we propose scheduling algorithms that aggregate the scheduling slack of instructions and communication slack of data values to exploit the low-power modes of functional units and interconnects. Finally, we present a synergistic combination of these algorithms that simultaneously saves energy in functional units and interconnects to improves the usability of clustered architectures by achieving better overall energy-performance trade-offs. Even with conservative estimates of the contribution of the functional units and interconnects to the overall processor energy consumption, the proposed combined scheme obtains on average 8% and 10% improvement in overall energy-delay product with 3.5% and 2% performance degradation for a 2-clustered and a 4-clustered machine, respectively. We present a detailed experimental evaluation of the proposed schemes. Our test bed uses the Trimaran compiler infrastructure. (C) 2012 Elsevier Inc. All rights reserved.

Making STMs Cache Friendly with Compiler Transformations

Software transactional memory (STM) is a promising programming paradigm for shared memory multithreaded programs. In order for STMs to be adopted widely for performance critical software, understanding and improving the cache performance of applications running on STM becomes increasingly crucial, as the performance gap between processor and memory continues to grow. In this paper, we present the most detailed experimental evaluation to date, of the cache behavior of STM applications and quantify the impact of the different STM factors on the cache misses experienced by the applications. We find that STMs are not cache friendly, with the data cache stall cycles contributing to more than 50% of the execution cycles in a majority of the benchmarks. We find that on an average, misses occurring inside the STM account for 62% of total data cache miss latency cycles experienced by the applications and the cache performance is impacted adversely due to certain inherent characteristics of the STM itself. The above observations motivate us to propose a set of specific compiler transformations targeted at making the STMs cache friendly. We find that STM's fine grained and application unaware locking is a major contributor to its poor cache behavior. Hence we propose selective Lock Data co-location (LDC) and Redundant Lock Access Removal (RLAR) to address the lock access misses. We find that even transactions that are completely disjoint access parallel, suffer from costly coherence misses caused by the centralized global time stamp updates and hence we propose the Selective Per-Partition Time Stamp (SPTS) transformation to address this. We show that our transformations are effective in improving the cache behavior of STM applications by reducing the data cache miss latency by 20.15% to 37.14% and improving execution time by 18.32% to 33.12% in five of the 8 STAMP applications.