Design of an HA2-based Escherichia coli expressed influenza immunogen that protects mice from pathogenic challenge

Influenza HA is the primary target of neutralizing antibodies during infection, and its sequence undergoes genetic drift and shift in response to immune pressure. The receptor binding HA1 subunit of HA shows much higher sequence variability relative to the metastable, fusion-active HA2 subunit, presumably because neutralizing antibodies are primarily targeted against the former in natural infection. We have designed an HA2-based immunogen using a protein minimization approach that incorporates designed mutations to destabilize the low pH conformation of HA2. The resulting construct (HA6) was expressed in Escherichia coli and refolded from inclusion bodies. Biophysical studies and mutational analysis of the protein indicate that it is folded into the desired neutral pH conformation competent to bind the broadly neutralizing HA2 directed monoclonal 12D1, not the low pH conformation observed in previous studies. HA6 was highly immunogenic in mice and the mice were protected against lethal challenge by the homologous A/HK/68 mouse-adapted virus. An HA6-like construct from another H3 strain (A/Phil/2/82) also protected mice against A/HK/68 challenge. Regions included in HA6 are highly conserved within a subtype and are fairly well conserved within a clade. Targeting the highly conserved HA2 subunit with a bacterially produced immunogen is a vaccine strategy that may aid in pandemic preparedness.

Generating synchronizable test sequences based on finite-statemachine with distributed ports

In the area of testing communication systems, the interfaces between systems to be tested and their testers have great impact on test generation and fault detectability. Several types of such interfaces have been standardized by the International Standardization Organization (ISO). A general distributed test architecture, containing distributed interfaces, has been presented in the literature for testing distributed systems based on the Open Distributing Processing (ODP) Basic Reference Model (BRM), which is a generalized version of ISO distributed test architecture. We study in this paper the issue of test selection with respect to such an test architecture. In particular, we consider communication systems that can be modeled by finite state machines with several distributed interfaces, called ports. A test generation method is developed for generating test sequences for such finite state machines, which is based on the idea of synchronizable test sequences. Starting from the initial effort by Sarikaya, a certain amount of work has been done for generating test sequences for finite state machines with respect to the ISO distributed test architecture, all based on the idea of modifying existing test generation methods to generate synchronizable test sequences. However, none studies the fault coverage provided by their methods. We investigate the issue of fault coverage and point out a fact that the methods given in the literature for the distributed test architecture cannot ensure the same fault coverage as the corresponding original testing methods. We also study the limitation of fault detectability in the distributed test architecture.

A new approach to the design of reinforcement schemes for learning automata

On introduit une nouvelle classe de schémas de renforcement des automates d'apprentissage utilisant les estimations des caractéristiques aléatoires de l'environnement. On montre que les algorithmes convergent en probabilité vers le choix optimal des actions. On présente les résultats de simulation et on suggère des applications à un environnement à plusieurs apprentissages

Common-mode filter design for PWM rectifier-based motor drives

A common-mode (CM) filter based on the LCL filter topology is proposed in this paper, which provides a parallel path for ground currents and which also restricts the magnitude of the EMI noise injected into the grid. The CM filter makes use of the components of a line to line LCL filter, which is modified to address the CM voltage with minimal additional components. This leads to a compact filtering solution. The CM voltage of an adjustable speed drive using a PWM rectifier is analyzed for this purpose. The filter design is based on the CM equivalent circuit of the drive system. The filter addresses the adverse effects of the PWM rectifier in an adjustable speed drive. Guidelines are provided on the selection of the filter components. Different variants of the filter topology are evaluated to establish the effectiveness of the proposed circuit. Experimental results based on EMI measurement on the grid side and the CM current measurement on the motor side are presented. These results validate the effectiveness of the filter.

Mechanism design for cost optimal PAC learning in the presence of strategic noisy annotators

We consider the problem of Probably Ap-proximate Correct (PAC) learning of a bi-nary classifier from noisy labeled exam-ples acquired from multiple annotators(each characterized by a respective clas-sification noise rate). First, we consider the complete information scenario, where the learner knows the noise rates of all the annotators. For this scenario, we derive sample complexity bound for the Mini-mum Disagreement Algorithm (MDA) on the number of labeled examples to be ob-tained from each annotator. Next, we consider the incomplete information sce-nario, where each annotator is strategic and holds the respective noise rate as a private information. For this scenario, we design a cost optimal procurement auc-tion mechanism along the lines of Myer-son’s optimal auction design framework in a non-trivial manner. This mechanism satisfies incentive compatibility property,thereby facilitating the learner to elicit true noise rates of all the annotators.

A neural network based automatic generation control design through reinforcement learning

This paper presents the design and implementation of a learning controller for the Automatic Generation Control (AGC) in power systems based on a reinforcement learning (RL) framework. In contrast to the recent RL scheme for AGC proposed by us, the present method permits handling of power system variables such as Area Control Error (ACE) and deviations from scheduled frequency and tie-line flows as continuous variables. (In the earlier scheme, these variables have to be quantized into finitely many levels). The optimal control law is arrived at in the RL framework by making use of Q-learning strategy. Since the state variables are continuous, we propose the use of Radial Basis Function (RBF) neural networks to compute the Q-values for a given input state. Since, in this application we cannot provide training data appropriate for the standard supervised learning framework, a reinforcement learning algorithm is employed to train the RBF network. We also employ a novel exploration strategy, based on a Learning Automata algorithm,for generating training samples during Q-learning. The proposed scheme, in addition to being simple to implement, inherits all the attractive features of an RL scheme such as model independent design, flexibility in control objective specification, robustness etc. Two implementations of the proposed approach are presented. Through simulation studies the attractiveness of this approach is demonstrated.

Design and implementation of a PC-based FPGA tester

A new range of programmable logic devices are revolutionizing the way complex digital hardware is designed and built all over the world. Being able to test these devices in order to validate and dynamically improve on the design is crucial. This paper describes a low-cost FPGA tester that can test SRAM based FPGAs in the laboratory.

V-Transform: “An Enhanced Polynomial Coefficient Based DC Test for Non-linear Analog Circuits

Abstract—DC testing of parametric faults in non-linear analog circuits based on a new transformation, entitled, V-Transform acting on polynomial coefficient expansion of the circuit function is presented. V-Transform serves the dual purpose of monotonizing polynomial coefficients of circuit function expansion and increasing the sensitivity of these coefficients to circuit parameters. The sensitivity of V-Transform Coefficients (VTC) to circuit parameters is up to 3x-5x more than sensitivity of polynomial coefficients. As a case study, we consider a benchmark elliptic filter to validate our method. The technique is shown to uncover hitherto untestable parametric faults whose sizes are smaller than 10 % of the nominal values. I.

Design, Development and Calibration of HTS Wire Based LOX Level Sensor Probe

For space applications, the weight of the liquid level sensors are of major concern as they affect the payload fraction and hence the cost. An attempt is made to design and test a light weight High Temperature Superconductor (HTS) wire based liquid level sensor for Liquid Oxygen (LOX) tank used in the cryostage of the spacecraft. The total resistance value measured of the HTS wire is inversely proportional to the liquid level. A HTS wire (SF12100) of 12mm width and 2.76m length without copper stabilizer has been used in the level sensor. The developed HTS wire based LOX level sensor is calibrated against a discrete diode array type level sensor. Liquid Nitrogen (LN2) and LOX has been used as cryogenic fluid for the calibration purpose. The automatic data logging for the system has been done using LabVIEW11. The net weight of the developed sensor is less than 1 kg.

Capability approach-based evaluation of a biomass cook-stove design

What is the scope and responsibilities of design? This work partially answers this by employing a normative approach to design of a biomass cook stove. This study debates on the sufficiency of existing design methodologies in the light of a capability approach. A case study of a biomass cook stove Astra Ole has elaborated the theoretical constructs of capability approach, which, in turn, has structured insights from field to evaluate the product. Capability approach based methodology is also prescriptively used to design the mould for rapid dissemination of the Astra Ole.

A Design for Performance Improvement of Clock Synchronization in WSNs using a TDMA-based MAC Protocol

Clock synchronization in a wireless sensor network (WSN) is quite essential as it provides a consistent and a coherent time frame for all the nodes across the network. Typically, clock synchronization is achieved by message passing using a contention-based scheme for media access, like carrier sense multiple access (CSMA). The nodes try to synchronize with each other, by sending synchronization request messages. If many nodes try to send messages simultaneously, contention-based schemes cannot efficiently avoid collisions. In such a situation, there are chances of collisions, and hence, message losses, which, in turn, affects the convergence of the synchronization algorithms. However, the number of collisions can be reduced with a frame based approach like time division multiple access (TDMA) for message passing. In this paper, we propose a design to utilize TDMA-based media access and control (MAC) protocol for the performance improvement of clock synchronization protocols. The basic idea is to use TDMA-based transmissions when the degree of synchronization improves among the sensor nodes during the execution of the clock synchronization algorithm. The design significantly reduces the collisions among the synchronization protocol messages. We have simulated the proposed protocol in Castalia network simulator. The simulation results show that the proposed protocol significantly reduces the time required for synchronization and also improves the accuracy of the synchronization algorithm.