Design and development of a self-supported polymer electrolyte fuel cell system with anodic dead-end operation

Design and operational details for a self-supported polymer electrolyte fuel cell (PEFC) system with anodic dead-end fuel supply and internally humidified cathodic oxidant flow are described. During the PEFC operation, nitrogen and water back diffuse across the Nafion membrane from the cathode to the anode and accumulate in the anode flow channels affecting stack performance. The accumulated inert species are flushed from the stack by purging the fuel cell stack with a timer-activated purge valve to address the aforesaid problem. To minimize the system complexity, stack is designed in such a way that all the inert species accumulate in only one cell called the purge cell. A pulsed purge sequence comprises opening the valve for purge duration followed by purge-valve closing for the hold period and repeating the sequence in cycles. Since self-humidification is inadequate to keep the membrane wet, the anodic dead-end-operated PEFC stack with composite membrane comprising perflourosulphonic acid (Nafion) and silica is employed for keeping the membrane humidified even while operating the stack with dry hydrogen and internally humidified air.

Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well

Design and implementation of spectrum sensing for cognitive radios with a frequency-hopping primary system

In this work, spectrum sensing for cognitive radios is considered in the presence of multiple Primary Users (PU) using frequency-hopping communication over a set of frequency bands. The detection performance of the Fast Fourier Transform (FFT) Average Ratio (FAR) algorithm is obtained in closed-form, for a given FFT size and number of PUs. The effective throughput of the Secondary Users (SU) is formulated as an optimization problem with a constraint on the maximum allowable interference on the primary network. Given the hopping period of the PUs, the sensing duration that maximizes the SU throughput is derived. The results are validated using Monte Carlo simulations. Further, an implementation of the FAR algorithm on the Lyrtech (now, Nutaq) small form factor software defined radio development platform is presented, and the performance recorded through the hardware is observed to corroborate well with that obtained through simulations, allowing for implementation losses. (C) 2015 Elsevier B.V. All rights reserved.

Design and implementation of a PC-based FPGA tester

A new range of programmable logic devices are revolutionizing the way complex digital hardware is designed and built all over the world. Being able to test these devices in order to validate and dynamically improve on the design is crucial. This paper describes a low-cost FPGA tester that can test SRAM based FPGAs in the laboratory.

The physics and technology of gallium antimonide: An emerging optoelectronic material

Recent advances in nonsilica fiber technology have prompted the development of suitable materials for devices operating beyond 1.55 mu m. The III-V ternaries and quaternaries (AlGaIn)(AsSb) lattice matched to GaSb seem to be the obvious choice and have turned out to be promising candidates for high speed electronic and long wavelength photonic devices. Consequently, there has been tremendous upthrust in research activities of GaSb-based systems. As a matter of fact, this compound has proved to be an interesting material for both basic and applied research. At present, GaSb technology is in its infancy and considerable research has to be carried out before it can be employed for large scale device fabrication. This article presents an up to date comprehensive account of research carried out hitherto. It explores in detail the material aspects of GaSb starting from crystal growth in bulk and epitaxial form, post growth material processing to device feasibility. An overview of the lattice, electronic, transport, optical and device related properties is presented. Some of the current areas of research and development have been critically reviewed and their significance for both understanding the basic physics as well as for device applications are addressed. These include the role of defects and impurities on the structural, optical and electrical properties of the material, various techniques employed for surface and bulk defect passivation and their effect on the device characteristics, development of novel device structures, etc. Several avenues where further work is required in order to upgrade this III-V compound for optoelectronic devices are listed. It is concluded that the present day knowledge in this material system is sufficient to understand the basic properties and what should be more vigorously pursued is their implementation for device fabrication. (C) 1997 American Institute of Physics.

Design and Implementation of a Flexible and Memory Efficient Operating System for Sensor Nodes

Sensor network nodes exhibit characteristics of both embedded systems and general-purpose systems.A sensor network operating system is a kind of embedded operating system, but unlike a typical embedded operating system, sensor network operatin g system may not be real time, and is constrained by memory and energy constraints. Most sensor network operating systems are based on event-driven approach. Event-driven approach is efficient in terms of time and space.Also this approach does not require a separate stack for each execution context. But using this model, it is difficult to implement long running tasks, like cryptographic operations. A thread based computation requires a separate stack for each execution context, and is less efficient in terms of time and space. In this paper, we propose a thread based execution model that uses only a fixed number of stacks. In this execution model, the number of stacks at each priority level are fixed. It minimizes the stack requirement for multi-threading environment and at the same time provides ease of programming. We give an implementation of this model in Contiki OS by separating thread implementation from protothread implementation completely. We have tested our OS by implementing a clock synchronization protocol using it.

RRI-GBT MULTI-BAND RECEIVER: MOTIVATION, DESIGN, AND DEVELOPMENT

We report the design and development of a self-contained multi-band receiver (MBR) system, intended for use with a single large aperture to facilitate sensitive and high time-resolution observations simultaneously in 10 discrete frequency bands sampling a wide spectral span (100-1500 MHz) in a nearly log-periodic fashion. The development of this system was primarily motivated by need for tomographic studies of pulsar polar emission regions. Although the system design is optimized for the primary goal, it is also suited for several other interesting astronomical investigations. The system consists of a dual-polarization multi-band feed (with discrete responses corresponding to the 10 bands pre-selected as relatively radio frequency interference free), a common wide-band radio frequency front-end, and independent back-end receiver chains for the 10 individual sub-bands. The raw voltage time sequences corresponding to 16 MHz bandwidth each for the two linear polarization channels and the 10 bands are recorded at the Nyquist rate simultaneously. We present the preliminary results from the tests and pulsar observations carried out with the Robert C. Byrd Green Bank Telescope using this receiver. The system performance implied by these results and possible improvements are also briefly discussed.