Switching transients in ferroelectric dicalcium strontium propionate (DSP) and azoxybenzene

The switching transients in dicalcium strontium propionate and azoxybenzene were studied by the use of the Merz method. It was observed that the switching time depends linearly on the applied electric field. Under similar electric fields, the switching processes in DSP and azoxybenzene are slower than in triglycine sulphate (TGS) at 27°C.

Switching transients in ferroelectric dicalcium strontium propionate (DSP) and Azoxybenzene

The ferroelectric polarization switching was studied in DSP single crystal and Azoxybenzene liquid film using the method described by Merz (1954). The DSP single crystal samples were in the form of plates 0.5 mm - 1.0 mm thick. The Azoxybenzene liquid film samples had a thickness from 0.025 mm - 0.125 mm. Switching in DSP was observed in the temperature range +7°C to -30°C, while in Azoxybenzene it was observed from 30°C to 70°C.

Vector control of permanent magnet synchronous motor using DSP controller

PMSM drive with high dynamic response is the attractive solution for servo applications like robotics, machine tools, electric vehicles. Vector control is widely accepted control strategy for PMSM control, which enables decoupled control of torque and flux, this improving the transient response of torque and speed. As the vector control demands exhaustive real time computations, so the present work is implemented using TI DSP 320C240. Presently position and speed controller have been successfully tested. The feedback information used is shaft (rotor) position from the incremental encoder and two motor currents. We conclude with the hope to extend the present experimental set up for further research related to PMSM applications.

Developement of DSP based educational kit for power electronics and drives

The educational kit was developed for power electronics and drives. The need and purpose of this kit is to train engineers with current technology of digital control in power electronics. The DSP is the natural choice as it is able to perform high speed calculations required in power electronics. The educational kit consists of a DSP platform using TI DSP TMS320C50 starter kit, an inverter and an induction machine-dc machine set. A set of experiments have been prepared so that DSP programming can be learned easily in a smooth fashion. Here the application presented is open loop V/F control of three phase induction using sine pulse width modulation technique.

Dual-DSP system for signal and image processing

The design of a dual-DSP microprocessor system and its application for parallel FFT and two-dimensional convolution are explained. The system is based on a master-salve configuration. Two ADSP-2101s are configured as slave processors and a PC/AT serves as the master. The master serves as a control processor to transfer the program code and data to the DSPs. The system architecture and the algorithms for the two applications, viz. FFT and two-dimensional convolutions, are discussed.

Synthesis of ASIPs for DSP algorithms

ASICs offer the best realization of DSP algorithms in terms of performance, but the cost is prohibitive, especially when the volumes involved are low. However, if the architecture synthesis trajectory for such algorithms is such that the target architecture can be identified as an interconnection of elementary parameterized computational structures, then it is possible to attain a close match, both in terms of performance and power with respect to an ASIC, for any algorithmic parameters of the given algorithm. Such an architecture is weakly programmable (configurable) and can be viewed as an application specific integrated processor (ASIP). In this work, we present a methodology to synthesize ASIPs for DSP algorithms. (C) 1999 Elsevier Science B.V. All rights reserved.

Adaptive Filtering Technique and DSP Based Implementation for High-Speed Distance Protection

The paper presents an adaptive Fourier filtering technique and a relaying scheme based on a combination of a digital band-pass filter along with a three-sample algorithm, for applications in high-speed numerical distance protection. To enhance the performance of above-mentioned technique, a high-speed fault detector has been used. MATLAB based simulation studies show that the adaptive Fourier filtering technique provides fast tripping for near faults and security for farther faults. The digital relaying scheme based on a combination of digital band-pass filter along with three-sample data window algorithm also provides accurate and high-speed detection of faults. The paper also proposes a high performance 16-bit fixed point DSP (Texas Instruments TMS320LF2407A) processor based hardware scheme suitable for implementation of the above techniques. To evaluate the performance of the proposed relaying scheme under steady state and transient conditions, PC based menu driven relay test procedures are developed using National Instruments LabVIEW software. The test signals are generated in real time using LabVIEW compatible analog output modules. The results obtained from the simulation studies as well as hardware implementations are also presented.

Synthesis of configurable architectures for DSP algorithms

ASICs offer the best realization of DSP algorithms in terms of performance, but the cost is prohibitive, especially when the volumes involved are low. However, if the architecture synthesis trajectory for such algorithms is such that the target architecture can be identified as an interconnection of elementary parameterized computational structures, then it is possible to attain a close match, both in terms of performance and power with respect to an ASIC, for any algorithmic parameters of the given algorithm. Such an architecture is weakly programmable (configurable) and can be viewed as an application specific instruction-set processor (ASIP). In this work, we present a methodology to synthesize ASIPs for DSP algorithms.

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip

Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the power and performance of the entire system. Further, the memory subsystem constitutes a major part (typically up to 70%) of the silicon area for the current day SoC. In this article, we address the on-chip memory architecture exploration for DSP processors which are organized as multiple memory banks, where banks can be single/dual ported with non-uniform bank sizes. In this paper we propose two different methods for physical memory architecture exploration and identify the strengths and applicability of these methods in a systematic way. Both methods address the memory architecture exploration for a given target application by considering the application's data access characteristics and generates a set of Pareto-optimal design points that are interesting from a power, performance and VLSI area perspective. To the best of our knowledge, this is the first comprehensive work on memory space exploration at physical memory level that integrates data layout and memory exploration to address the system objectives from both hardware design and application software development perspective. Further we propose an automatic framework that explores the design space identifying 100's of Pareto-optimal design points within a few hours of running on a standard desktop configuration.

Electron- Spin-Resonance studies of phase transitions in double propionates

Detailed ESR investigations of Mn2+ substituting for Ca2+ in Ca2Sr(C2H5COO)6, (DSP) and Ca2Pb(C2H5COO)6, (DLP) and Ca2Ba(C2H5COO)6, (DBP), in single crystals and powders, over the temperature range from 300°C to -180°C have been carried out to study the successive phase transitions in these compounds. Spectra have been analyzed in terms of axial spin Hamiltonians and the temperature dependences of the parameters studied. Across the I-II transition, new physically and chemically inequivalent sites appear indicating the disappearance of the diad axes on which the propionate groups are located, bringing out the connection between the motional states of the propionate groups and the occurrence of ferroelectricity. The II-III transition also causes chemically inequivalent sites to develop, indicating that the transitions may not be isomorphous as believed previously. Similarities and dissimilarities of the ESR spectra of DLP, DSP and DBP are discussed in relation to the phase transitions.

ESR studies of phase transitions in double propionates

Detailed ESR investigations of Mn2+ substituting for Ca2+ in Ca2Sr(C2H5COO)6 (DSP), Ca2Pb(C2H5COO)6 (DLP) and Ca2Ba(C2H5COO)6 (DBP), in single crystals and powders, over the temperature range from 200°C to -180°C have been carried out to study the successive phase transitions in these compounds. (DSP: [Tetragonal] ← 8.5°C → [tetragonal, ferroelectric] [tetragonal] ← -169°C → [monoclinic, ferroelectric]; DLP : [tetragonal] ← 60°C → [tetragonal, ferroelectric] ← -71.5°C → [monoclinic, ferroelectric]; [Cubic] ← -6°C → [orthorhombic] ← -75°C → [?]). Spectra have been analysed in terms of axial spin Hamiltonians and the temperature dependences of the parameters studied. In DSP and DLP across the I ↔ II transition, new physically and chemically inequivalent sites appear indicating the disappearance of the diad axes on which the propionate groups are located, bringing out the connection between the motional states of the propionate groups and the occurence of ferroelectricity. The II ↔ III transition also causes chemically inequivalent sites to develop, indicating that the transitions may not be isomorphous as believed previously. In DBP, the -6°C transition leads to (i) a doubling of both physically and chemically inequivalent sites (ii) a small (150 G at -6°C to 170 G at -8°C), but abrupt change in the magnitude of the zero-field splitting tensor D, and (iii) displacements of the orientations of the D tensors. Results are interpreted in terms of alternate rotations of the oxygen octahedra, showing participation of the carboxyl oxygens in the transition. No drastic changes in the parameters occur across the -75°C transition consistent with its second order nature. Similarities and dissimilarities of the ESR spectra of the three compounds in relation to the phase transitions, are discussed.

RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router

A polymorphic ASIC is a runtime reconfigurable hardware substrate comprising compute and communication elements. It is a ldquofuture proofrdquo custom hardware solution for multiple applications and their derivatives in a domain. Interoperability between application derivatives at runtime is achieved through hardware reconfiguration. In this paper we present the design of a single cycle Network on Chip (NoC) router that is responsible for effecting runtime reconfiguration of the hardware substrate. The router design is optimized to avoid FIFO buffers at the input port and loop back at output crossbar. It provides virtual channels to emulate a non-blocking network and supports a simple X-Y relative addressing scheme to limit the control overhead to 9 bits per packet. The 8times8 honeycomb NoC (RECONNECT) implemented in 130 nm UMC CMOS standard cell library operates at 500 MHz and has a bisection bandwidth of 28.5 GBps. The network is characterized for random, self-similar and application specific traffic patterns that model the execution of multimedia and DSP kernels with varying network loads and virtual channels. Our implementation with 4 virtual channels has an average network latency of 24 clock cycles and throughput of 62.5% of the network capacity for random traffic. For application specific traffic the latency is 6 clock cycles and throughput is 87% of the network capacity.

Robust flight stability and control for micro air vehicles.

This chapter presents the real time validation of fixed order robust 112 controller designed for the lateral stabilisation of a micro air vehicle named Sarika2. Digital signal processor (DSP) based onboard computer named flight instrumentation controller (FIC) is designed to operate under automatic or manual mode. FIC gathers data from multitude of sensors and is capable of closed loop control to enable autonomous flight. Fixed order lateral H-2 controller designed with the features such as incorporation of level I flying qualities, gust alleviation and noise rejection is coded on to the FIC. Challenging real time hardware in loop simulation (HILS) is done with dSPACE1104 RTI/RTW. Responses obtained from the HILS are compared with those obtained from the offline simulation. Finally, flight trials are conducted to demonstrate the satisfactory performance of the closed loop system. The generic design methodology developed is applicable to all classes of Mini and Micro air vehicles.

Minimizing buffer requirements under rate-optimal schedule in regular dataflow networks

Large-grain synchronous dataflow graphs or multi-rate graphs have the distinct feature that the nodes of the dataflow graph fire at different rates. Such multi-rate large-grain dataflow graphs have been widely regarded as a powerful programming model for DSP applications. In this paper we propose a method to minimize buffer storage requirement in constructing rate-optimal compile-time (MBRO) schedules for multi-rate dataflow graphs. We demonstrate that the constraints to minimize buffer storage while executing at the optimal computation rate (i.e. the maximum possible computation rate without storage constraints) can be formulated as a unified linear programming problem in our framework. A novel feature of our method is that in constructing the rate-optimal schedule, it directly minimizes the memory requirement by choosing the schedule time of nodes appropriately. Lastly, a new circular-arc interval graph coloring algorithm has been proposed to further reduce the memory requirement by allowing buffer sharing among the arcs of the multi-rate dataflow graph. We have constructed an experimental testbed which implements our MBRO scheduling algorithm as well as (i) the widely used periodic admissible parallel schedules (also known as block schedules) proposed by Lee and Messerschmitt (IEEE Transactions on Computers, vol. 36, no. 1, 1987, pp. 24-35), (ii) the optimal scheduling buffer allocation (OSBA) algorithm of Ning and Gao (Conference Record of the Twentieth Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, Charleston, SC, Jan. 10-13, 1993, pp. 29-42), and (iii) the multi-rate software pipelining (MRSP) algorithm (Govindarajan and Gao, in Proceedings of the 1993 International Conference on Application Specific Array Processors, Venice, Italy, Oct. 25-27, 1993, pp. 77-88). Schedules generated for a number of random dataflow graphs and for a set of DSP application programs using the different scheduling methods are compared. The experimental results have demonstrated a significant improvement (10-20%) in buffer requirements for the MBRO schedules compared to the schedules generated by the other three methods, without sacrificing the computation rate. The MBRO method also gives a 20% average improvement in computation rate compared to Lee's Block scheduling method.