A Simple Multiple pulsewidth Modulated AC Multiple Chopper

A simple multiple pulsewidth modulated (MPWM) ac chopper using power transistors for 3-¿ power control is discussed. 120° chopping period is used for main transistors so that the circuit can accommodate resistive and lagging or leading power factor loads. Only 1-¿ sensing is used for 3-¿ control. An alternate economical power and control schemes for 3-¿ MPWM ac choppers suitable only for resistive loads is also suggested. The experimental results for 12 choppings per cycle are given.

A Simple Multiple Pulsewidth Modulated AC Choppe

A simple multiple pulsewidth modulated (MPWM) ac chopper using power transistors for 3-ý power control is discussed. 120ý chopping period is used for main transistors so that the circuit can accommodate resistive and lagging or leading power factor loads. Only 1-ý sensing is used for 3-ý control. An alternate economical power and control schemes for 3-ý MPWM ac choppers suitable only for resistive loads is also suggested. The experimental results for 12 choppings per cycle are given.

A linear ramp control circuit using two LM 556 dual timers

A simple linear ramp control circuit, suitable for use with force-commutated thyrister circuits is discussed here. The circuit is based on only two IM 558 dual timer iCs, operating from a single 15 V supply. The reset terminals facilitate inhibition of the output of any stage. The use of this circuit in a thyristor chopper operating at 400 Hz 13 described.

An Advanced Gate Driver for Insulated Gate Bipolar Transistors to Eliminate Dead-time Induced Distortions in Inverter Output

Dead-time is introduced between the gating signals to the top and bottom switches in a voltage source inverter (VSI) leg, to prevent shoot through fault due to the finite turn-off times of IGBTs. The dead-time results in a delay when the incoming device is an IGBT, resulting in error voltage pulses in the inverter output voltage. This paper presents the design, fabrication and testing of an advanced gate driver, which eliminates dead-time and consequent output distortion. Here, the gating pulses are generated such that the incoming IGBT transition is not delayed and shoot-through is also prevented. The various logic units of the driver card and fault tolerance of the driver are verified through extensive tests on different topologies such as chopper, half-bridge and full-bridge inverter, and also at different conditions of load. Experimental results demonstrate the improvement in the load current waveform quality with the proposed circuit, on account of elimination of dead-time.