54 resultados para Buck converters

em Indian Institute of Science - Bangalore - Índia


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This letter proposes a simple tuning algorithm for digital deadbeat control based on error correlation. By injecting a square-wave reference input and calculating the correlation of the control error, a gain correction for deadbeat control is obtained. The proposed solution is simple, it requires a short tuning time, and it is suitable for different DC-DC converter topologies. Simulation and experimental results on synchronous buck converters confirm the properties of the proposed tuning algorithm.

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High power converters are used in variable speed induction motor drive applications. Riding through a short term power supply glitch is becoming an important requirement in these power converters. The power converter uses a large number of control circuit boards for its operation. The control power supply need to ensure that any glitch in the grid side does not affect any of these control circuit boards. A power supply failure of these control cards results in shut down of the entire system. The paper discusses the ride through system developed to overcome voltage sags and short duration outages at the power supply terminals of the control cards in these converters. A 240VA non-isolated, bi-directional buck-boost converter has been designed to be used along with a stack of ultracapacitors to achieve the same. A micro-controller based digital control platform made use of to achieve the control objective. The design of the ultracapacitor stack and the bidirectional converter is described the performance of the experimental set-up is evaluated.

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This paper discusses dynamic modeling of non-isolated DC-DC converters (buck, boost and buck-boost) under continuous and discontinuous modes of operation. Three types of models are presented for each converter, namely, switching model, average model and harmonic model. These models include significant non-idealities of the converters. The switching model gives the instantaneous currents and voltages of the converter. The average model provides the ripple-free currents and voltages, averaged over a switching cycle. The harmonic model gives the peak to peak values of ripple in currents and voltages. The validity of all these models is established by comparing the simulation results with the experimental results from laboratory prototypes, at different steady state and transient conditions. Simulation based on a combination of average and harmonic models is shown to provide all relevant information as obtained from the switching model, while consuming less computation time than the latter.

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Circuits for realizing serial quaternary-to-analogue converters (QACs) are proposed in this paper. Three techniques are presented based on Shannon-Rack decoder, sample/hold serial digital-to-analogue converter and cyclic digital-to-analogue converter. Circuits for the generation of control signals and the multiplexer required in the realization of the QACs are also described. A comparison of the three methods is made.

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A simple ramp control firing circuit, suitable for use with fully controlled, line-commutated thyristor bridge circuits, is discussed here. This circuit uses very few components and generates the synchronized firing pulses in a simple way. It operates from a single 15 V Supply and has an inherent pulse inhibit facility. This circuit provides the synchronized firing pulses for both thyristors of the same limb in a bridge. To ensure reliability, wide triggering pulses are used, which are modulated to pass through the pulse transformers1 and demodulated before being fed to the thyristor gates. The use of throe such circuits only for a three-phase bridge is discussed.

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A simple ramp control firing circuit, suitable for use with fully controlled, line-commutated thyristor bridge circuits, is discussed here. This circuit uses very few components and generates the synchronized firing pulses in a simple way. It operates from a single 15 V Supply and has an inherent pulse inhibit facility. This circuit provides the synchronized firing pulses for both thyristors of the same limb in a bridge. To ensure reliability, wide triggering pulses are used, which are modulated to pass through the pulse transformers1 and demodulated before being fed to the thyristor gates. The use of throe such circuits only for a three-phase bridge is discussed.

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A simple firing delay circuit for 3-φ fully controlled bridge using a phase locked loop is described. The circuit uses very few components and is an improved scheme over the existing methods. The use of this circuit in three-phase thyristor converters and 'circulating current free' mode dual converters is described.

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A novel ZVS auxiliary switch commutated variation for all DGDC converter topologies has been proposed in 2006. With proper designation of the circuit variables (throw current I and the pole voltage V), all these converters are seen to be governed by an identical set of equations. With idealized switches, the steady-state performance is obtainable in an analytical form. The conversion ratio of the converter topologies is obtained. A generalized equivalent circuit emerges for all these converters from the steady-state conversion ratio. It also provides a dynamic model as well. With these generalized steady-state equivalent circuits, small signal analysis of these converters may be carried out readily. It enables one to use the familiar state space averaged results of the standard PWM DGDC converters for the resonant counterparts. Th dc and ac models reveals that dc and low frequency behaviour of the proposed family of converters is similiar to that of its PWM parent

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A simple firing delay circuit for 3-φ fully controlled bridge using a phase locked loop is described. The circuit uses very few components and is an improved scheme over the existing methods. The use of this circuit in three-phase thyristor converters and 'circulating current free' mode dual converters is described.

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A procedure has been given for minimizing the total output noise of a Generalized Impedance Converter (GIC), subject to constraints dictated by signal handling capability of the Operational Amplifiers and ease of microcircuit fabrication. The noise reduction is achieved only by the adjustment of RC elements of the GIC, and the total output noise after optimization in the example cited is close to the theoretical lower limit. The output noise of a higher-order filter can be reduced by RC-optimizing the individual GIC's of the active realization. Experimental results on a 20–24 kHz channel bank band-pass filter demonstrate the effectiveness of the above procedure.

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Active-clamp dc-dc converters are pulsewidth-modulated converters having two switches featuring zero-voltage switching at frequencies beyond 100 kHz. Generalized equivalent circuits valid for steady-state and dynamic performance have been proposed for the family of active-clamp converters. The active-clamp converter is analyzed for its dynamic behavior under current control in this paper. The steady-state stability analysis is presented. On account of the lossless damping inherent in the active-clamp converters, it appears that the stability region in the current-controlled active-clamp converters get extended for duty ratios, a little greater than 0.5, unlike in conventional hard-switched converters. The conventional graphical approach fails to assess the stability of current-controlled active-clamp converters due to the coupling between the filter inductor current and resonant inductor current. An analysis that takes into account the presence of the resonant elements is presented to establish the condition for stability. This method correctly predicts the stability of the current-controlled active-clamp converters. A simple expression for the maximum duty cycle for subharmonic free operation is obtained. The results are verified experimentally.

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Multilevel converters have been under research and development for more than three decades and have found successful industrial application. However, this is still a technology under development, and many new contributions and new commercial topologies have been reported in the last few years. The aim of this paper is to group and review these recent contributions, in order to establish the current state of the art and trends of the technology, to provide readers with a comprehensive and insightful review of where multilevel converter technology stands and is heading. This paper first presents a brief overview of well-established multilevel converters strongly oriented to their current state in industrial applications to then center the discussion on the new converters that have made their way into the industry. In addition, new promising topologies are discussed. Recent advances made in modulation and control of multilevel converters are also addressed. A great part of this paper is devoted to show nontraditional applications powered by multilevel converters and how multilevel converters are becoming an enabling technology in many industrial sectors. Finally, some future trends and challenges in the further development of this technology are discussed to motivate future contributions that address open problems and explore new possibilities.

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Neutral point clamped (NPC), three level converters with insulated gate bipolar transistor devices are very popular in medium voltage, high power applications. DC bus short circuit protection is usually done, using the sensed voltage across collector and emitter (i.e., V-CE sensing), of all the devices in a leg. This feature is accommodated with the conventional gate drive circuits used in the two level converters. The similar gate drive circuit, when adopted for NPC three level converter protection, leads to false V-CE fault signals for inner devices of the leg. The paper explains the detailed circuit behavior and reasons, which result in the occurrence of such false V-CE fault signals. This paper also illustrates that such a phenomenon shows dependence on the power factor of the supplied three-phase load. Finally, experimental results are presented to support the analysis. It is shown that the problem can be avoided by blocking out the V-CE sense fault signals of the inner devices of the leg.

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The soft switching converters evolved through the resonant load, resonant switch, resonant transition and active clamp converters to eliminate switching losses in power converters. This paper briefly presents the operating principle of the new family of soft transition converters; the methodology of design of these converters is presented through an example. In the proposed family of converters, the switching transitions of both the main switch and auxiliary switch are lossless.When these converters are analysed in terms of the pole current and throw voltage, the defining equations of all converters belonging to this family become identical.Such a description allows one to define simple circuit oriented model for these converters. These circuit models help in evaluating the steady state and dynamic model of these converters. The standard dynamic performance functions of the converters are readily obtainable from this model. This paper presents these dynamic models and verifies the same through measurements on a prototype converter.