Advances in the analysis and design of concrete structures, metal containments and liner plate for extreme loads

The material presented in this paper summarizes the progress that has been made in the analysis, design, and testing of concrete structures. The material is summarized in the following documents: 1. Part I - Containment Design Criteria and Loading Combinations - J.D. Stevenson (Stevenson and Associates, Cleveland, Ohio, USA) 2. Part II - Reinforced and Prestressed Concrete Behavior - J. Eibl and M. Curbach (Karlsruhe University, Karlsruhe, Germany) 3. Part III - Concrete Containment Analysis, Design and Related Testing - T.E. Johnson and M.A. Daye (Bechtel Power Corporation, Gaithersburg, Maryland USA) 4. Part IV - Impact and Impulse Loading and Response Prediction - J.D. Riera (School of Engineering - UFRGS, Porto Alegre, RS, Brazil) 5. Part V - Metal Containments and Liner Plate Systems - N.J. Krutzik (Siemens AG, Offenbach Am Main, Germany) 6. Part VI - Prestressed Reactor Vessel Design, Testing and Analysis - J. Nemet (Austrian Research Center, Seibersdorf, Austria) and K.T.S. Iyengar (Indian Institute of Science, Bangalore, India).

Analyzing Cache Performance Bottlenecks of STM Applications and addressing them with Compiler's help

Software transactional memory (STM) is a promising programming paradigm for shared memory multithreaded programs as an alternative to traditional lock based synchronization. However adoption of STM in mainstream software has been quite low due to its considerable overheads and its poor cache/memory performance. In this paper, we perform a detailed study of the cache behavior of STM applications and quantify the impact of different STM factors on the cache misses experienced by the applications. Based on our analysis, we propose a compiler driven Lock-Data Colocation (LDC), targeted at reducing the cache overheads on STM. We show that LDC is effective in improving the cache behavior of STM applications by reducing the dcache miss latency and improving execution time performance.

NUcache: A Multicore Cache Organization Based on Next-Use Distance

In this work, we propose a new organization for the last level shared cache of a rnulticore system. Our design is based on the observation that the Next-Use distance, measured in terms of intervening misses between the eviction of a line and its next use, for lines brought in by a given delinquent PC falls within a predictable range of values. We exploit this correlation to improve the performance of shared caches in multi-core architectures by proposing the NUcache organization.