Reuse of treated sewage in Delhi city: Microbial evaluation of STPs and reuse options

Microbiological quality of the treated wastewater is an important parameter for its reuse. The data oil the Fecal Coliform (FC) and Fecal Streptococcus (FS) at different stages of treatment in the Sewage Treatment Plants (STPs) in Delhi watershed is not available, therefore in the present study microbial profiling of STPs was carried out to assess the effluent quality for present and future reuse options. This Study further evaluates the water quality profiles at different stages of treatment for 16 STPs in Delhi city. These STPs are based on conventional Activated Sludge Process (ASP), extended aeration, physical, chemical and biological treatment (BIOFORE), Trickling Filter and Oxidation Pond. The primary effluent quality produced from most of the STPs was suitable for Soil Aquifer Treatment (SAT). Extended Hydraulic Retention Time (HRT) as a result Of low inflow to the STPS Was responsible for high turbidity, COD and BODs removal. Conventional ASP based STPs achieved 1.66 log FC and 1.06 log FS removal. STPs with extended aeration treatment process produced better quality effluent with maximum 4 log order reduction in FC and FS levels. ``Kondli'' and ``Nilothi'' STPs employing ASP, produced better quality secondary effluent as compared to other STPs based oil similar treatment process. Oxidation Pond based STPs showed better FC and FS removals, whereas good physiochemical quality was achieved during the first half of the treatment. Based upon physical, chemical and microbiological removal efficiencies, actual integrated efficiency (IEa) of each STP was determined to evaluate its Suitability for reuse for irrigation purposes. Except Mehrauli'' and ``Oxidation Pond'', effluents from all other STPs require tertiary treatment for further reuse. Possible reuse options, depending Upon the geographical location, proximity of facilities of potential users based oil the beneficial uses, and sub-soil types, etc. for the Delhi city have been investigated, which include artificial groundwater recharge, aquaculture, horticulture and industrial uses Such as floor washing, boiler feed, and cooling towers, etc. (C) 2009 Elsevier B.V. All rights reserved.

SPSA algorithms with measurement reuse

Four algorithms, all variants of Simultaneous Perturbation Stochastic Approximation (SPSA), are proposed. The original one-measurement SPSA uses an estimate of the gradient of objective function L containing an additional bias term not seen in two-measurement SPSA. As a result, the asymptotic covariance matrix of the iterate convergence process has a bias term. We propose a one-measurement algorithm that eliminates this bias, and has asymptotic convergence properties making for easier comparison with the two-measurement SPSA. The algorithm, under certain conditions, outperforms both forms of SPSA with the only overhead being the storage of a single measurement. We also propose a similar algorithm that uses perturbations obtained from normalized Hadamard matrices. The convergence w.p. 1 of both algorithms is established. We extend measurement reuse to design two second-order SPSA algorithms and sketch the convergence analysis. Finally, we present simulation results on an illustrative minimization problem.

A System-C based Micro architectural Exploration Framework for Latency, Power and Performance Trade-offs of On-Chip Interconnection

We describe a System-C based framework we are developing, to explore the impact of various architectural and microarchitectural level parameters of the on-chip interconnection network elements on its power and performance. The framework enables one to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. We provide preliminary results of using this framework to study the power, latency and throughput of a 4x4 multi-core processing array using mesh, torus and folded torus, for two different communication patterns of dense and sparse linear algebra. The traffic consists of both Request-Response messages (mimicing cache accesses)and One-Way messages. We find that the average latency can be reduced by increasing the pipeline depth, as it enables higher link frequencies. We also find that there exists an optimum degree of pipelining which minimizes energy-delay product.

On the Limits of Spatial Reuse and Cooperative Communication for Dense Wireless Networks

We consider a dense ad hoc wireless network comprising n nodes confined to a given two dimensional region of fixed area. For the Gupta-Kumar random traffic model and a realistic interference and path loss model (i.e., the channel power gains are bounded above, and are bounded below by a strictly positive number), we study the scaling of the aggregate end-to-end throughput with respect to the network average power constraint, P macr, and the number of nodes, n. The network power constraint P macr is related to the per node power constraint, P macr, as P macr = np. For large P, we show that the throughput saturates as Theta(log(P macr)), irrespective of the number of nodes in the network. For moderate P, which can accommodate spatial reuse to improve end-to-end throughput, we observe that the amount of spatial reuse feasible in the network is limited by the diameter of the network. In fact, we observe that the end-to-end path loss in the network and the amount of spatial reuse feasible in the network are inversely proportional. This puts a restriction on the gains achievable using the cooperative communication techniques studied in and, as these rely on direct long distance communication over the network.

Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation

Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an optimizing compiler, they do not succeed many a time due to limited knowledge of run-time data. In this paper we examine instruction reuse of integer ALU and load instructions in network processing applications. Specifically, this paper attempts to answer the following questions: (1) How much of instruction reuse is inherent in network processing applications?, (2) Can reuse be improved by reducing interference in the reuse buffer?, (3) What characteristics of network applications can be exploited to improve reuse?, and (4) What is the effect of reuse on resource contention and memory accesses? We propose an aggregation scheme that combines the high-level concept of network traffic i.e. "flows" with a low level microarchitectural feature of programs i.e. repetition of instructions and data along with an architecture that exploits temporal locality in incoming packet data to improve reuse. We find that for the benchmarks considered, 1% to 50% of instructions are reused while the speedup achieved varies between 1% and 24%. As a side effect, instruction reuse reduces memory traffic and can therefore be considered as a scheme for low power.

Reuse, recycle to de-bloat software

Most Java programmers would agree that Java is a language that promotes a philosophy of “create and go forth”. By design, temporary objects are meant to be created on the heap, possibly used and then abandoned to be collected by the garbage collector. Excessive generation of temporary objects is termed “object churn” and is a form of software bloat that often leads to performance and memory problems. To mitigate this problem, many compiler optimizations aim at identifying objects that may be allocated on the stack. However, most such optimizations miss large opportunities for memory reuse when dealing with objects inside loops or when dealing with container objects. In this paper, we describe a novel algorithm that detects bloat caused by the creation of temporary container and String objects within a loop. Our analysis determines which objects created within a loop can be reused. Then we describe a source-to-source transformation that efficiently reuses such objects. Empirical evaluation indicates that our solution can reduce upto 40% of temporary object allocations in large programs, resulting in a performance improvement that can be as high as a 20% reduction in the run time, specifically when a program has a high churn rate or when the program is memory intensive and needs to run the GC often.

Architectural plan of transcriptional regulation in Mycobacterium tuberculosis

Transcriptional regulation enables adaptation in bacteria. Typically, only a few transcriptional events are well understood, leaving many others unidentified. The recent genome-wide identification of transcription factor binding sites in Mycobacterium tuberculosis has changed this by deciphering a molecular road-map of transcriptional control, indicating active events and their immediate downstream effects.