Worker piping triggers hissing for coordinated colony defence in the dwarf honeybee Apis florea

Defending a large social insect colony containing several thousands of workers requires the simultaneous action of many individuals. Ideally this action involves communication between the workers, enabling coordinated action and a fast response. The Asian dwarf honeybee, Apis florea, is a small honeybee with an open nesting habit and a comparatively small colony size, features that leave them particularly exposed to predators. We describe here a novel defence response of these bees in which the emission of an initial warning signal from one individual (“piping”) is followed 0.3 to 0.7 seconds later by a general response from a large number of bees (“hissing”). Piping is audible to the human ear, with a fundamental frequency of 384 ± 31Hz and lasting for 0.82 ± 0.35 seconds. Hissing is a broad band, noisy signal, clearly audible to the human observer and produced by slight but visible movements of the bees' wings. Hissing begins in individuals close to the piping bee, spreads rapidly to neighbours and results in an impressive coordinated crescendo occasionally involving the entire colony. Piping and hissing are accompanied by a marked decrease, or even cessation, of worker activities such as forager dancing and departures from the colony. We show that whereas hissing of the colony can be elicited without piping, the sequential and correlated piping and hissing response is specific to the presence of potential predators close to the colony. We suggest that the combined audio-visual effect of the hissing might deter small predators, while the cessation of flight activity could decrease the risk of predation by birds and insects which prey selectively on flying bees.

Energy Reduction in SRAM using Dynamic Voltage and Frequency Management

This paper describes a dynamic voltage frequency control scheme for a 256 X 64 SRAM block for reducing the energy in active mode and stand-by mode. The DVFM control system monitors the external clock and changes the supply voltage and the body bias so as to achieve a significant reduction in energy. The behavioral model of the proposed DVFM control system algorithm is described and simulated in HDL using delay and energy parameters obtained through SPICE simulation. The frequency range dictated by an external controller is 100 MHz to I GHz. The supply voltage of the complete memory system is varied in steps of 50 mV over the range of 500 mV to IV. The threshold voltage range of operation is plusmn100 mV around the nominal value, achieving 83.4% energy reduction in the active mode and 86.7% in the stand-by mode. This paper also proposes a energy replica that is used in the energy monitor subsystem of the DVFM system.

Compiler-Directed Frequency and Voltage Scaling for a Multiple Clock Domain

Multiple Clock Domain processors provide an attractive solution to the increasingly challenging problems of clock distribution and power dissipation. They allow their chips to be partitioned into different clock domains, and each domain’s frequency (voltage) to be independently configured. This flexibility adds new dimensions to the Dynamic Voltage and Frequency Scaling problem, while providing better scope for saving energy and meeting performance demands. In this paper, we propose a compiler directed approach for MCD-DVFS. We build a formal petri net based program performance model, parameterized by settings of microarchitectural components and resource configurations, and integrate it with our compiler passes for frequency selection.Our model estimates the performance impact of a frequency setting, unlike the existing best techniques which rely on weaker indicators of domain performance such as queue occupancies(used by online methods) and slack manifestation for a particular frequency setting (software based methods).We evaluate our method with subsets of SPECFP2000,Mediabench and Mibench benchmarks. Our mean energy savings is 60.39% (versus 33.91% of the best software technique)in a memory constrained system for cache miss dominated benchmarks, and we meet the performance demands.Our ED2 improves by 22.11% (versus 18.34%) for other benchmarks. For a CPU with restricted frequency settings, our energy consumption is within 4.69% of the optimal.

Dark Matter Halo Properties as Deduced from the Observed H I Scale Height Data, in The Low-Frequency Radio Universe

We use the HΙ scale height data along with the HΙ rotation curve as constraints to probe the shape and density profile of the dark matter halos of M31 (Andromeda) and the superthin, low surface brightness (LSB) galaxy UGC 07321. We model the galaxy as a two component system of gravitationally-coupled stars and gas subjected to the force field of a dark matter halo. For M31, we get a flattened halo which is required to match the outer galactic HΙ scale height data, with our best-fit axis ratio (0.4) lying at the most oblate end of the distributions obtained from cosmological simulations. For UGC 07321, our best-fit halo core radius is only slightly larger than the stellar disc scale length, indicating that the halo is important even at small radii in this LSB galaxy. The high value of the gas velocity dispersion required to match the scale height data can explain the low star-formation rate of this galaxy.

An improved sapce phasor based current hysteresis controller with reduced switching frequency variations using variable parabolic bands

A current error space phasor based simple hysteresis controller is proposed in this paper to control the switching frequency variation in two-level pulsewidth-modulation (PWM) inverter-fed induction motor (IM) drives. A parabolic boundary for the current error space phasor is suggested for the first time to obtain the switching frequency spectrum for output voltage with hysteresis controller similar to the constant switching frequency voltage-controlled space vector PWM-based IM drive. A novel concept of online variation of this parabolic boundary, which depends on the operating speed of motor, is presented. A generalized technique that determines the set of unique parabolic boundaries for a two-level inverter feeding any given induction motor is described. The sector change logic is self-adaptive and is capable of taking the drive up to the six-step mode if needed. Steady-state and transient performance of proposed controller is experimentally verified on a 3.7-kW IM drive in the entire speed range. Close resemblance of the simulation and experimental results is shown.

Multicode STBC in Frequency-Selective Fading

Multicode operation in space-time block coded (STBC) multiple input multiple output (MIMO) systems can provide additional degrees of freedom in code domain to achieve high data rates. In such multicode STBC systems, the receiver experiences code domain interference (CDI) in frequency selective fading. In this paper, we propose a linear parallel interference cancellation (LPIC) approach to cancel the CDI in multicode STBC signals in frequency selective fading. The proposed detector first performs LPIC followed by STBC decoding. We present an SINK for the proposed detector. We evaluate the bit error rate (BER) performance of the system, and show that the proposed detector effectively cancels the CDI and achieves improved error performance. Our BER results further illustrate how the combined effect of interference cancellation, transmit diversity, and RAKE diversity affects the performance of the system.

Reduced Rate Ultra Low Delay Audio Coder using Multistage Vector Quantization

Communication applications are usually delay restricted, especially for the instance of musicians playing over the Internet. This requires a one-way delay of maximum 25 msec and also a high audio quality is desired at feasible bit rates. The ultra low delay (ULD) audio coding structure is well suited to this application and we investigate further the application of multistage vector quantization (MSVQ) to reach a bit rate range below 64 Kb/s, in a scalable manner. Results at 32 Kb/s and 64 Kb/s show that the trained codebook MSVQ performs best, better than KLT normalization followed by a simulated Gaussian MSVQ or simulated Gaussian MSVQ alone. The results also show that there is only a weak dependence on the training data, and that we indeed converge to the perceptual quality of our previous ULD coder at 64 Kb/s.

Analysis and Synthesis of Reverberation for Parametric Stereo Audio

We propose a parametric stereo coding analysis and synthesis directly in the MDCT domain using an analysis by synthesis parameter estimation. The stereo signal is represented by an equalized sum signal and spatialization parameters. Equalized sum signal and the spatialization parameters are obtained by sub-band analysis in the MDCT domain. The de-correlated signal required for the stereo synthesis is also generated in the MDCT domain. Subjective evaluation test using MUSHRA shows that the synthesized stereo signal is perceptually satisfactory and comparable to the state of the art parametric coders.