Transmission electron microscopy study of domain structures in ferroelectric SrBi2Nb2O9 ceramics

A transmission electron microscopy study has been carried out on the domain structures of SrBi2Nb2O9 (SBN) ferroelectric ceramics which belong to the Aurivillius family of bismuth layered perovskite oxides. SBN is a potential candidate for Ferroelectric Random access memory (FeRAM) applications. The 90° ferroelectric domains and antiphase boundaries (APBs) were identified with dark field imaging techniques using different superlattice reflections which arise as a consequence of octahedral rotations and cationic shifts. The 90° domain walls are irregular in shape without any faceting. The antiphase boundaries are less dense compared to that of SrBi2Ta2O9(SBT). The electron microscopy observations are correlated with the polarization fatigue nature of the ceramic where the domain structures possibly play a key role in the fatigue- free behavior of the Aurivillius family of ferroelectric oxides.

Design and Implementation of a Flexible and Memory Efficient Operating System for Sensor Nodes

Sensor network nodes exhibit characteristics of both embedded systems and general-purpose systems.A sensor network operating system is a kind of embedded operating system, but unlike a typical embedded operating system, sensor network operatin g system may not be real time, and is constrained by memory and energy constraints. Most sensor network operating systems are based on event-driven approach. Event-driven approach is efficient in terms of time and space.Also this approach does not require a separate stack for each execution context. But using this model, it is difficult to implement long running tasks, like cryptographic operations. A thread based computation requires a separate stack for each execution context, and is less efficient in terms of time and space. In this paper, we propose a thread based execution model that uses only a fixed number of stacks. In this execution model, the number of stacks at each priority level are fixed. It minimizes the stack requirement for multi-threading environment and at the same time provides ease of programming. We give an implementation of this model in Contiki OS by separating thread implementation from protothread implementation completely. We have tested our OS by implementing a clock synchronization protocol using it.

Electrical and magneto-resistance of Co/CNT/epoxy thin film for strain and magnetic field sensing

Cobalt and iron nanoparticles are doped in carbon nanotube (CNT)/polymer matrix composites and studied for strain and magnetic field sensing properties. Characterization of these samples is done for various volume fractions of each constituent (Co and Fe nanoparticles and CNTs) and also for cases when only either of the metallic components is present. The relation between the magnetic field and polarization-induced strain are exploited. The electronic bandgap change in the CNTs is obtained by a simplified tight-binding formulation in terms of strain and magnetic field. A nonlinear constitutive model of glassy polymer is employed to account for (1) electric bias field dependent softening/hardening (2) CNT orientations as a statistical ensemble and (3) CNT volume fraction. An effective medium theory is then employed where the CNTs and nanoparticles are treated as inclusions. The intensity of the applied magnetic field is read indirectly as the change in resistance of the sample. Very small magnetic fields can be detected using this technique since the resistance is highly sensitive to strain. Its sensitivity due to the CNT volume fraction is also discussed. The advantage of this sensor lies in the fact that it can be molded into desirable shape and can be used in fabrication of embedded sensors where the material can detect external magnetic fields on its own. Besides, the stress-controlled hysteresis of the sample can be used in designing memory devices. These composites have potential for use in magnetic encoders, which are made of a magnetic field sensor and a barcode.

Java Memory Model aware Software validation

The Java Memory Model (JMM) provides a semantics of Java multithreading for any implementation platform. The JMM is defined in a declarative fashion with an allowed program execution being defined in terms of existence of "commit sequences" (roughly, the order in which actions in the execution are committed). In this work, we develop OpMM, an operational under-approximation of the JMM. The immediate motivation of this work lies in integrating a formal specification of the JMM with software model checkers. We show how our operational memory model description can be integrated into a Java Path Finder (JPF) style model checker for Java programs.

Memory Architecture Exploration Framework for Cache Based Embedded SoC

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

Bit Steering In The Minimization Of Control Memory In Microprogrammed Digital-Computers

This correspondence presents an algorithm for microprogram control memory width minimization with the bit steering technique. The necessary and sufficient conditions to detect the steerability of two mutually exclusive sets of microcommands are established. The algorithm encodes the microcommands of the sets with a bit steering common part and also extends the theory to multiple (more than two) sets of microcommands.

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.

Evolution of crystallinity of free gold agglomerates and shape transformation

We report the shape evolution of free gold agglomerates with different morphologies that transform to ellipsoidal and then to spherical shapes during the heating cycle. The shape transformation is associated with a structural transition from polycrystalline to single crystalline. The structural transition temperature is shown to be dependent on the final size of the particles and not on the initial morphologies of the agglomerates. It is also shown that the transition occurs well below the melting temperature which is in contrast with the melt-freeze process reported in the literature.