Comparison of one cycle control of charge and current for bi-directional boost rectifiers

Classical control and one cycle control of current are popular methods used to modulate pulses in active rectifiers for ac-dc power conversion. One cycle control has lower control complexity and can be implemented using linear analog circuits when compared with the classical approach. However, it also suffers from problems such as instability and offsets in current that is severe at light load conditions. A control strategy for bidirectional boost rectifiers based on one cycle control of charge is proposed for that overcomes these limitations. The integral of sensed current, which represents charge, is compared with a non-linear carrier, which is modified for ac-dc power conversion. This generates the gating signals for the switching devices. The modifications required for the control law governing one cycle control of charge is derived in the paper. Detailed simulation studies are carried out to compare one cycle control of current with the proposed method for ac-dc power conversion, which are validated on a laboratory hardware prototype.

A multi-winding transformer based power converter topology for a growing DC Micro-grid structure

A DC micro-grid essentially consists of power ports, bidirectional power converter and a controller structure that enables the control of dynamic power flow. In this paper, a prototype of a micro-grid structure using a recently proposed multi-winding transformer based power converter has been implemented. The power converter topology is further extended to multiple transformer cores in order to form a growing micro-grid structure. Additionally, modifications have been made in order to incorporate a battery charge controller with the main power circuit. All the other advantages of the power converter and its control scheme are still preserved.

Common-mode voltage eliminated three-level inverter using a three-level flying-capacitor inverter and cascaded H-bridge

This paper proposes a new 3 level common mode voltage eliminated inverter using an inverter structure formed by cascading a H-Bridge with a three-level flying capacitor inverter. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the results are experimentally verified. This system has an advantage that if one of devices in the H-Bridge fails, the system can still be operated as a normal 3 level inverter mode at full power. This inverter has many advantages like use of single DC-supply, making it possible for a back to back grid-tied converter application, improved reliability etc.

Apparatus and method for heat-run test on high-power PWM converters with low energy expenditure

Before installation, a voltage source converter is usually subjected to heat-run test to verify its thermal design and performance under load. For heat-run test, the converter needs to be operated at rated voltage and rated current for a substantial length of time. Hence, such tests consume huge amount of energy in case of high-power converters. Also, the capacities of the source and loads available in the research and development (R&D) centre or the production facility could be inadequate to conduct such tests. This paper proposes a method to conduct heat-run tests on high-power, pulse width modulated (PWM) converters with low energy consumption. The experimental set-up consists of the converter under test and another converter (of similar or higher rating), both connected in parallel on the ac side and open on the dc side. Vector-control or synchronous reference frame control is employed to control the converters such that one draws certain amount of reactive power and the other supplies the same; only the system losses are drawn from the mains. The performance of the controller is validated through simulation and experiments. Experimental results, pertaining to heat-run tests on a high-power PWM converter, are presented at power levels of 25 kVA to 150 kVA.

A Seventeen-level Inverter With a Single DC-link For Motor Drives

In the present paper, a novel topology for generating a 17-level inverter using three-level flying capacitor inverter and cascaded H-bridge modules with floating capacitors. The proposed circuit is analyzed and various aspects of it are presented in the paper. This circuit is experimentally verified and the results are shown. The stability of the capacitor balancing algorithm has been verified during sudden acceleration. This circuit has many pole voltage redundancies. This circuit has an advantage of balancing all the capacitor voltages instantaneously by switching through the redundancies. Another advantage of this topology is its ability to generate all the 17 pole voltages from a single DC link which enables back to back converter operation. Also, the proposed inverter can be operated at all load power factors and modulation indices. Another advantage is, if one of the H-bridges fail, the inverter can still be operated at full load with reduced number of levels.

Investigation of dielectric relaxation, Jahn-Teller distortion, and magnetic ordering in Y substituted Pr1-xYxMnO3 (0.1 <= x <= 0.4)

We report structural, magnetic, and dielectric properties of the perovskite compound Pr1-xYxMnO3 (0.1 <= x <= 0.4) studied using dc magnetization, ac susceptibility, neutron powder diffraction, and dielectric techniques. These compounds crystallize in orthorhombic space group (Pnma) in the temperature range 5-300 K. The Mn-O-Mn bond angle decreases with the Y substitution along with an increase in the Jahn-Teller distortion. The Jahn-Teller distortion for Pr0.9Y0.1MnO3 shows an anomalous change near 50 K, below which it falls sharply. Neutron powder diffraction patterns of all reported compositions at low temperature constitute additional magnetic Bragg peaks that suggest magnetic ordering. Magnetic reflections were indexed in the nuclear lattice with the propagation vector k = (0, 0, 0). Rietveld refinement of powder patterns conform to A type antiferromagnetic ordering where moments are aligned ferromagnetically in a-c plane and coupled nearly antiferromagnetically along b-axis resulting in a net ferromagnetic component along the b-direction. The antiferromagnetic transition temperature was deduced from dc magnetization and ac susceptibility data. The transition temperature decreases by nearly 22 K (from 81 K to 59 K) as yttrium content (x) increases from 0.1 to 0.4. Measurements reveal strong frequency dispersion in dielectric constant and dielectric loss. Activation energy and relaxation time are estimated from the Arrhenius plot. It is further shown that relaxation behaviour is altered with yttrium doping concentration. (C) 2015 AIP Publishing LLC.

Experimental results on low cost microcontroller based DC drive implementation

This paper presents the experimental results for an attractive control scheme implementation using an 8 bit microcontroller. The power converter involved is a 3 phase full controlled bridge rectifier. A single quadrant DC drive has been realized and results have been presented for both open and closed loop implementations.

A Simple Hysteretic Energy Harvesting Method for Nonneutral AC Switches in Load Automation

This paper presents a simple hysteretic method to obtain the energy required to operate the gate-drive, sensors, and other circuits within nonneutral ac switches intended for use in load automated buildings. The proposed method features a switch-mode low part-count self-powered MOSFET ac switch that achieves efficiency and load current THD figures comparable to those of an externally gate-driven switch built using similar MOSFETS. The fundamental operation of the method is explained in detail, followed by the modifications required for practical implementation. Certain design rules that allow the method to accommodate a wide range of single-phase loads from 10 VA to 1 kVA are discussed, along with an efficiency enhancement feature based on inherent MOSFET characteristics. The limitations and side effects of the method are also mentioned according to their levels of severity. Finally, experimental results obtained using a prototype sensor switch are presented, along with a performance comparison of the prototype with an externally gate-driven MOSFET switch.

Design Optimization of Thin-Film Transistors Based on a Metal-Substrate-Semiconductor Architecture for High DC Voltage Sensing

We discuss the potential application of high dc voltage sensing using thin-film transistors (TFTs) on flexible substrates. High voltage sensing has potential applications for power transmission instrumentation. For this, we consider a gate metal-substrate-semiconductor architecture for TFTs. In this architecture, the flexible substrate not only provides mechanical support but also plays the role of the gate dielectric of the TFT. Hence, the thickness of the substrate needs to be optimized for maximizing transconductance, minimizing mechanical stress, and minimizing gate leakage currents. We discuss this optimization, and develop n-type and p-type organic TFTs using polyvinyldene fluoride as the substrate-gate insulator. Circuits are also realized to achieve level shifting, amplification, and high drain voltage operation.

Reduced common-mode voltage operation of a new seven-level hybrid multilevel inverter topology with a single DC voltage source

In this study, analysis of extending the linear modulation range of a zero common-mode voltage (CMV) operated n-level inverter by allowing reduced CMV switching is presented. A new hybrid seven-level inverter topology with a single DC supply is also presented in this study and inverter operation for zero and reduced CMV is analysed. Each phase of the inverter is realised by cascading two three-level flying capacitor inverters with a half-bridge module in between. Proposed inverter topology is operated with zero CMV for modulation index <86% and is operated with a CMV magnitude of V-dc/18 to extend the modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilising the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology.