A New Family of Soft Transition Converters: Design Example and Dynamic Model

The soft switching converters evolved through the resonant load, resonant switch, resonant transition and active clamp converters to eliminate switching losses in power converters. This paper briefly presents the operating principle of the new family of soft transition converters; the methodology of design of these converters is presented through an example. In the proposed family of converters, the switching transitions of both the main switch and auxiliary switch are lossless.When these converters are analysed in terms of the pole current and throw voltage, the defining equations of all converters belonging to this family become identical.Such a description allows one to define simple circuit oriented model for these converters. These circuit models help in evaluating the steady state and dynamic model of these converters. The standard dynamic performance functions of the converters are readily obtainable from this model. This paper presents these dynamic models and verifies the same through measurements on a prototype converter.

Digital Deadbeat Control Tuning for dc-dc Converters Using Error Correlation

This letter proposes a simple tuning algorithm for digital deadbeat control based on error correlation. By injecting a square-wave reference input and calculating the correlation of the control error, a gain correction for deadbeat control is obtained. The proposed solution is simple, it requires a short tuning time, and it is suitable for different DC-DC converter topologies. Simulation and experimental results on synchronous buck converters confirm the properties of the proposed tuning algorithm.

A new family of soft transition converters: Design and dynamic model

The soft switching converters evolved through the resonant load, resonant switch, resonant transition and active clamp converters to eliminate switching losses in power converters. This paper briefly presents the operating principle of the new family of soft transition converters; the methodology of design of these converters is presented through an example. In the proposed family of converters, the switching transitions of both the main switch and auxiliary switch are lossless. When these converters are analysed in terms of the pole current and throw voltage, the defining equations of all converters belonging to this family become identical.Such a description allows one to define simple circuit oriented model for these converters. These circuit models help in evaluating the steady state and dynamic model of these converters. The standard dynamic performance functions of the converters are readily obtainable from this model. This paper presents these dynamic models and verifies the same through measurements on a prototype converter.

Analog/RF Built-in-Self-Test Subsystem for a Mobile Broadcast Video Receiver in 65-nm CMOS

A built-in-self-test (BIST) subsystem embedded in a 65-nm mobile broadcast video receiver is described. The subsystem is designed to perform analog and RF measurements at multiple internal nodes of the receiver. It uses a distributed network of CMOS sensors and a low bandwidth, 12-bit A/D converter to perform the measurements with a serial bus interface enabling a digital transfer of measured data to automatic test equipment (ATE). A perturbation/correlation based BIST method is described, which makes pass/fail determination on parts, resulting in significant test time and cost reduction.

Steady-State Stability of Current-Mode Active-Clamp ZVS DC-DC Converters

Active-clamp dc-dc converters are pulsewidth-modulated converters having two switches featuring zero-voltage switching at frequencies beyond 100 kHz. Generalized equivalent circuits valid for steady-state and dynamic performance have been proposed for the family of active-clamp converters. The active-clamp converter is analyzed for its dynamic behavior under current control in this paper. The steady-state stability analysis is presented. On account of the lossless damping inherent in the active-clamp converters, it appears that the stability region in the current-controlled active-clamp converters get extended for duty ratios, a little greater than 0.5 unlike in conventional hard-switched converters. The conventional graphical approach fails to assess the stability of current-controlled active-clamp converters, due to the coupling between the filter inductor current and resonant inductor current. An analysis that takes into account the presence of the resonant elements is presented to establish the condition for stability. This method correctly predicts the stability of the current-controlled active-clamp converters. A simple expression for the maximum duty cycle for subharmonic-free operation is obtained. The results are verified experimentally.

Optimal Parameterized Policies for Resource Allocation in Communication Networks

The problem of finding optimal parameterized feedback policies for dynamic bandwidth allocation in communication networks is studied. We consider a queueing model with two queues to which traffic from different competing flows arrive. The queue length at the buffers is observed every T instants of time, on the basis of which a decision on the amount of bandwidth to be allocated to each buffer for the next T instants is made. We consider two different classes of multilevel closed-loop feedback policies for the system and use a two-timescale simultaneous perturbation stochastic approximation (SPSA) algorithm to find optimal policies within each prescribed class. We study the performance of the proposed algorithm on a numerical setting and show performance comparisons of the two optimal multilevel closedloop policies with optimal open loop policies. We observe that closed loop policies of Class B that tune parameters for both the queues and do not have the constraint that the entire bandwidth be used at each instant exhibit the best results overall as they offer greater flexibility in parameter tuning. Index Terms — Resource allocation, dynamic bandwidth allocation in communication networks, two-timescale SPSA algorithm, optimal parameterized policies. I.

Improved utilisation of an HF transformer in DC–AC application

Power conversion using high frequency (HF) link converters is popular because of compact size and light weight of highfrequency transformer. This study focuses on improved utilisation of HF transformer in DC–AC applications. In practical application, the operating condition of the power converter deviates significantly from the designed considerations. These deviating factors are commutation requirements (dead-time, overlap), mismatch in device drops and presence of the fundamental frequency in load current. As a result, the HF transformer handles some amount of low-frequency components (including DC) other than desired HF components. This causes the operating point in B-H curve to shift away from its normal or idealised position and hence results poor utilisation of the HF transformer and unwanted losses. This study investigates the nature of the problem with experimental determination of approximate lumped parameter modelling and saturation behaviour (B-H curve) of the HF transformer. A simple closed-loop control algorithm with online tuning of the controller parameters is proposed to improve the utilisation of the isolation transformer. The simulation and experimental results are presented.

Input voltage modulated high voltage DC power supply topology for pulsed load applications

High voltage power supplies for radar applications are investigated which are subjected to pulsed load with stringent specifications. In the proposed solution, power conversion is done in two stages. A low power-high frequency converter modulates the input voltage of a high power-low frequency converter. This method satisfies all the performance specifications and takes care of the critical aspects of HV transformer.

Digital Dead Time Logic and Protection Circuitry for PWM Voltage Source Converters

Power semiconductor devices have finite turn on and turn off delays that may not be perfectly matched. In a leg of a voltage source converter, the simultaneous turn on of one device and the turn off of the complementary device will cause a DC bus shoot through, if the turn off delay is larger than the turn on delay time. To avoid this situation it is common practice to blank the two complementary devices in a leg for a small duration of time while switching, which is called dead time. This paper proposes a logic circuit for digital implementation required to control the complementary devices of a leg independently and at the same time preventing cross conduction of devices in a leg, and while providing accurate and stable dead time. This implementation is based on the concept of finite state machines. This circuit can also block improper PWM pulses to semiconductor switches and filters small pulses notches below a threshold time width as the narrow pulses do not provide any significant contribution to average pole voltage, but leads to increased switching loss. This proposed dead time logic has been implemented in a CPLD and is implemented in a protection and delay card for 3- power converters.

Gate Drive Card for High Power Three Phase PWM Converters

Gate driver is an integral part of every power converter, drives the power semiconductor devices and also provides protection for the switches against short-circuit events and over-voltages during shut down. Gate drive card for IGBTs and MOSFETs with basic features can be designed easily by making use of discrete electronic components. Gate driver ICs provides attractive features in a single package, which improves reliability and reduces effort of design engineers. Either case needs one or more isolated power supplies to drive each power semiconductor devices and provide isolation to the control circuitry from the power circuit. The primary emphasis is then to provide simplified and compact isolated power supplies to the gate drive card with the requisite isolation strength and which consumes less space, and for providing thermal protection to the power semiconductor modules for 3-� 3 wire or 4 wire inverters.

High powerACmotor drives: Status review and work at IISc

A variety of solutions are available today from industry for high power variable speed AC motor drive applications, starting from a power rating of a few 100 kW to several 10’s of Megawatts. These drives can be classified on the basis of the electrical motor, the power converter and the control technique. The main drive types are reviewed.The salient features of each type of drive are pointed out along with their industrial applications.Following this, some research at IISc which has applications in high power drives is described briefly.

Beat frequency oscillations in the output voltage of high voltage DC power supplies under pulsed loading

High voltage power supplies for radar applications are investigated, which are subjected to pulsed load (125 kHz and 10% duty cycle) with stringent specifications (<0.01% regulation, efficiency>85%, droop<0.5 V/micro-sec.). As good regulation and stable operation requires the converter to be switched at much higher frequency than the pulse load frequency, transformer poses serious problems of insulation failure and higher losses. Few converter topologies are proposed to tackle these problems. A study is made regarding the beat frequency oscillations that may exist with pulsed loading. It is illustrated with respect to the proposed converter topologies. Methods are proposed to eliminate or minimize these oscillations.

Five-level inverter voltage-space phasor generation for an open-end winding induction motor drive

A topology for voltage-space phasor generation equivalent to a five-level inverter for an open-end winding induction motor is presented. The open-end winding induction motor is fed from both ends by two three-level inverters. The three-level inverters are realised by cascading two two-level inverters. This inverter scheme does not experience neutral-point fluctuations. Of the two three-level inverters only one will be switching at any instant in the lower speed ranges. In the multilevel carrier-based SPWM used for the proposed drive, a progressive discrete DC bias depending on the speed range is given to the reference wave to reduce the inverter switchings. The drive is implemented and tested with a 1 HP open-end winding induction motor and experimental results are presented.

Application of Solar Powered High Voltage Discharge Plasma for NOX Removal in Diesel Engine Exhaust

This paper proposes a compact electric discharge plasma source for controlling NOX emission in diesel engine exhaust. Boost converter is used to boost to solar powered battery voltage to 24V, further an automobile ignition coil was used to generate the high voltage pulse using fly-back topology. This design is aimed at retrofitting the existing catalytic converters with pulse assisted cleaning technique. In this paper we bring out a relative comparison of discharge plasma and plasma-adsorbent process at different gas flow rates. Activated alumina was used as adsorbent. The main emphasis is laid on the development of a compact pulse source from 12V battery, which is powered by the solar, for the removal of NOX from the filtered diesel engine exhaust.

Application of Solar Powered High Voltage Discharge Plasma for NOX Rem

This paper proposes a compact electric discharge plasma source for controlling NOX emission in diesel engine exhaust. Boost converter is used to boost to solar powered battery voltage to 24V, further an automobile ignition coil was used to generate the high voltage pulse using fly-back topology. This design is aimed at retrofitting the existing catalytic converters with pulse assisted cleaning technique. In this paper we bring out a relative comparison of discharge plasma and plasma-adsorbent process at different gas flow rates. Activated alumina was used as adsorbent. The main emphasis is laid on the development of a compact pulse source from 12V battery, which is powered by the solar, for the removal of NOX from the filtered diesel engine exhaust.