Co-Exploration of NLA Kernels and Specification of Compute Elements in Distributed Memory CGRAs

Coarse Grained Reconfigurable Architectures (CGRA) are emerging as embedded application processing units in computing platforms for Exascale computing. Such CGRAs are distributed memory multi- core compute elements on a chip that communicate over a Network-on-chip (NoC). Numerical Linear Algebra (NLA) kernels are key to several high performance computing applications. In this paper we propose a systematic methodology to obtain the specification of Compute Elements (CE) for such CGRAs. We analyze block Matrix Multiplication and block LU Decomposition algorithms in the context of a CGRA, and obtain theoretical bounds on communication requirements, and memory sizes for a CE. Support for high performance custom computations common to NLA kernels are met through custom function units (CFUs) in the CEs. We present results to justify the merits of such CFUs.

Growth and characteristics of amorphous Sb2Se3 thin films of various thicknesses for memory switching applications

Thin films of different thicknesses in the range of 200-720 nm have been deposited on glass substrates at room temperature using thermal evaporation technique. The structural investigations revealed that the as-deposited films are amorphous in nature. The surface roughness of the films shows an increasing trend at higher thickness of the films. The surface roughness of the films shows an increasing trend at higher thickness of the films. Interference fringes in the transmission spectra of these films suggest that the films are fairly smooth and uniform. The optical absorption in Sb2Se3 film is described using indirect transition and the variation in band gaps is explained on the basis of defects and disorders in the chalcogenide systems. Raman spectrum confirms the increase of orderliness with film thickness. From the I-V characteristics, a memory type switching is observed whose threshold voltage increases with film thickness. (C) 2015 Elsevier B.V. All rights reserved.

An efficient design of serial and parallel memory using Quantum dot cellular automata

Quantum cellular automata (QCA) is a new technology in the nanometer scale and has been considered as one of the alternative to CMOS technology. In this paper, we describe the design and layout of a serial memory and parallel memory, showing the layout of individual memory cells. Assuming that we can fabricate cells which are separated by 10nm, memory capacities of over 1.6 Gbit/cm2 can be achieved. Simulations on the proposed memories were carried out using QCADesigner, a layout and simulation tool for QCA. During the design, we have tried to reduce the number of cells as well as to reduce the area which is found to be 86.16sq mm and 0.12 nm2 area with the QCA based memory cell. We have also achieved an increase in efficiency by 40%.These circuits are the building block of nano processors and provide us to understand the nano devices of the future.

All Inorganic Spin-Coated Nanoparticle-Based Capacitive Memory Devices

We demonstrate all inorganic, robust, cost-effective, spin-coated, two-terminal capacitive memory metal-oxide nanoparticle-oxide-semiconductor devices with cadmium telluride nanoparticles sandwiched between aluminum oxide phosphate layers to form the dielectric memory stack. Using a novel high-speed circuit to decouple reading and writing, experimentally measured memory windows, programming voltages, retention times, and endurance are comparable with or better than the two-terminal memory devices realized using other fabrication techniques.