Flow Investigation of Linear Cluster Plug Nozzle

Computational and experimental tools have been used to understand the linear cluster plug nozzle flowfield for a range of pressure ratios. The experimental cluster configuration is arrived at from a linear plug nozzle by introducing splitter plates in the primary nozzle, and computational analysis of corresponding geometry is also carried out. The flow development on the plug surface has been analyzed for two different cluster module spacings. The interactions between the cluster module jets is a complex one with a three-dimensional shock structure because of the differential end condition the shock experiences on the plug wall and freejet boundary. A prominent streamwise vorticity resulting from curvature of the shock is also seen along the length of the plug downstream of the module junctions. The out-of-phase wave interactions occurring along the module centerline and the splitter plate centerline, resulting in a wavy surface-limiting streamline pattern, particularly at lower pressure ratios, is explained.

Reduced common-mode voltage operation of a new seven-level hybrid multilevel inverter topology with a single DC voltage source

In this study, analysis of extending the linear modulation range of a zero common-mode voltage (CMV) operated n-level inverter by allowing reduced CMV switching is presented. A new hybrid seven-level inverter topology with a single DC supply is also presented in this study and inverter operation for zero and reduced CMV is analysed. Each phase of the inverter is realised by cascading two three-level flying capacitor inverters with a half-bridge module in between. Proposed inverter topology is operated with zero CMV for modulation index <86% and is operated with a CMV magnitude of V-dc/18 to extend the modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilising the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology.