MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip

The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded DSP is complex and usually custom designed with multiple banks of single-ported or dual ported on-chip scratch pad memory and multiple banks of off-chip memory. Building software for such large complex memories with many of the software components as individually optimized software IPs is a big challenge. In order to obtain good performance and a reduction in memory stalls, the data buffers of the application need to be placed carefully in different types of memory. In this paper we present a unified framework (MODLEX) that combines different data layout optimizations to address the complex DSP memory architectures. Our method models the data layout problem as multi-objective genetic algorithm (GA) with performance and power being the objectives and presents a set of solution points which is attractive from a platform design viewpoint. While most of the work in the literature assumes that performance and power are non-conflicting objectives, our work demonstrates that there is significant trade-off (up to 70%) that is possible between power and performance.

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.

VLSI Implementation of Spatial prediction Based Image Compression Scheme

We propose the design and implementation of hardware architecture for spatial prediction based image compression scheme, which consists of prediction phase and quantization phase. In prediction phase, the hierarchical tree structure obtained from the test image is used to predict every central pixel of an image by its four neighboring pixels. The prediction scheme generates an error image, to which the wavelet/sub-band coding algorithm can be applied to obtain efficient compression. The software model is tested for its performance in terms of entropy, standard deviation. The memory and silicon area constraints play a vital role in the realization of the hardware for hand-held devices. The hardware architecture is constructed for the proposed scheme, which involves the aspects of parallelism in instructions and data. The processor consists of pipelined functional units to obtain the maximum throughput and higher speed of operation. The hardware model is analyzed for performance in terms throughput, speed and power. The results of hardware model indicate that the proposed architecture is suitable for power constrained implementations with higher data rate

Hydrothermal synthesis of CdTe QDs: Their luminescence quenching in the presence of bio-molecules and observation of bistable memory effect in CdTe QD/PEDOT:PSS heterostructure

We report one-pot hydrothermal synthesis of nearly mono-disperse 3-mercaptopropionic acid capped water-soluble cadmium telluride (CdTe) quantum dots (QDs) using an air stable Te source. The optical and electrical characteristics were also studied here. It was shown that the hydrothermal synthesis could be tuned to synthesize nano structures of uniform size close to nanometers. The emissions of the CdTe QDs thus synthesized were in the range of 500-700 nm by varying the duration of synthesis. The full width at half maximum (FWHM) of the emission peaks is relatively narrow (40-90 nm), which indicates a nearly uniform distribution of QD size. The structural and optical properties of the QDs were characterized by transmission electron microscopy (TEM), photoluminescence (PL) and Ultraviolet-visible (UV-Vis) spectroscopy. The photoluminescence quenching of CdTe QDs in the presence of L-cysteine and DNA confirms its biocompatibility and its utility for biosensing applications. The room temperature current-voltage characteristics of QD film on ITO coated glass substrate show an electrically induced switching between states with high and low conductivities. The phenomenon is explained on the basis of charge confinement in quantum dots. (C) 2011 Elsevier B.V. All rights reserved.

High-temperature deformation processing maps for a NiTiCu shape memory alloy

The properties of widely used Ni-Ti-based shape memory alloys (SMAs) are highly sensitive to the underlying microstructure. Hence, controlling the evolution of microstructure during high-temperature deformation becomes important. In this article, the ``processing maps'' approach is utilized to identify the combination of temperature and strain rate for thermomechanical processing of a Ni(42)Ti(50)Cu(8) SMA. Uniaxial compression experiments were conducted in the temperature range of 800-1050 degrees C and at strain rate range of 10(-3) and 10(2) s(-1). Two-dimensional power dissipation efficiency and instability maps have been generated and various deformation mechanisms, which operate in different temperature and strain rate regimes, were identified with the aid of the maps and complementary microstructural analysis of the deformed specimens. Results show that the safe window for industrial processing of this alloy is in the range of 800-850 degrees C and at 0.1 s(-1), which leads to grain refinement and strain-free grains. Regions of the instability were identified, which result in strained microstructure, which in turn can affect the performance of the SMA.

Spin-polarized STM spectra of Dirac electrons on the surface of a topological insulator

We provide a theory for the tunneling conductance G(V) of Dirac electrons on the surface of a topological insulator as measured by a spin-polarized scanning tunneling microscope tip for low-bias voltages V. We show that if the in-plane rotational symmetry on the surface of the topological insulator is broken by an external field that does not couple to spin directly (such as an in-plane electric field), G(V) exhibits an unconventional dependence on the direction of the magnetization of the tip, i.e., it acquires a dependence on the azimuthal angle of the magnetization of the tip. We also show that G(V) can be used to measure the magnitude of the local out-of-plane spin orientation of the Dirac electrons on the surface. We explain the role of the Dirac electrons in this unconventional behavior and suggest experiments to test our theory.

Setting up Multilingual Information Repository: A case Study with EPrints.org Software

Today 80 % of the content on the Web is in English, which is spoken by only 8% of the World population and 5% of Indian population. There is wealth of useful content in the various languages of the world other than English, which can be made available on the Internet. But, to date, for various reasons most of it is not yet available on the Internet. India itself has 18 officially recognized languages and scores of dialects. Although the medium of instruction for most of the higher education and research in India is English, substantial amount of literature by way of novels, textbooks, scholarly information are being generated in the other languages in the country. Many of the e-governance initiatives are in the respective state languages. In the past, support for different languages by the operating systems and the software packages were not very encouraging. However, with the advent of Unicode technology, operating systems and software packages are supporting almost all the major languages of the world that have scripts. In the work reported in this paper, we have explained the configuration changes that are needed for Eprints.org software to store multilingual content and to create a multilingual user interface.

Scalable processes for fabricating non-volatile memory devices using self-assembled 2D arrays of gold nanoparticles as charge storage nodes

We propose robust and scalable processes for the fabrication of floating gate devices using ordered arrays of 7 nm size gold nanoparticles as charge storage nodes. The proposed strategy can be readily adapted for fabricating next generation (sub-20 nm node) non-volatile memory devices.