176 resultados para SILICON NANOWIRES


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Interdiffusion study is conducted in the V-Si system to determine integrated diffusion coefficients of the phases. Activation energy values are calculated from the experiments conducted at different temperatures. The average values are found to be 208, 240 and 141 kJ/mol, respectively, for the V(3)Si, V(5)Si(3) and VSi(2) phases. The low activation energy for the VSi(2) phase indicates very high concentration of defects or the significant contribution from the grain boundary diffusion. The error in calculation of diffusion parameters from a very thin phase layer in a multiphase diffusion couple is discussed. Further the data available in the literature in this system is compared and the problems in the indirect methodology followed previously to calculate the diffusion parameters are discussed.

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The severe wear of a near eutectic aluminium silicon alloy is explored using a range of electron microscopic, spectroscopic and diffraction techniques to identify the residually strained and unstrained regions, microcracks and oxidized regions in the subsurface. In severe wear the contact pressure exceeds the elastic shakedown limit. Under this condition the primary and eutectic silicon particles fragment drastically. The fragments are transported by the matrix as it undergoes incremental straining with each cyclic contact at the asperity level. The grains are refined from similar to 2000 nm in the bulk to 30 nm in the near surface region. A large reduction in the interparticle distance compared with that for a milder stage of wear gives rise to high strain gradients which contribute to an enhancement of the dislocation density. The resulting regions of very high strain in the boundaries of the recrystallized grains as well as within the subgrains lead to the formation of microvoidskracks. This is accompanied by the formation of brittle oxides at these subsurface interfaces due to enhanced diffusion of oxygen. We believe that the abundance of such microcracks in the near surface region, primed by severe plastic deformation, is what distinguishes a severe wear regime from mild wear. (C) 2011 Acta Materialia Inc. Published by Elsevier Ltd. All rights reserved.

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Size and strain rate effects are among several factors which play an important role in determining the response of nanostructures, such as their deformations, to the mechanical loadings. The mechanical deformations in nanostructure systems at finite temperatures are intrinsically dynamic processes. Most of the recent works in this context have been focused on nanowires [1, 2], but very little attention has been paid to such low dimensional nanostructures as quantum dots (QDs). In this contribution, molecular dynamics (MD) simulations with an embedded atom potential method(EAM) are carried out to analyse the size and strain rate effects in the silicon (Si) QDs, as an example. We consider various geometries of QDs such as spherical, cylindrical and cubic. We choose Si QDs as an example due to their major applications in solar cells and biosensing. The analysis has also been focused on the variation in the deformation mechanisms with the size and strain rate for Si QD embedded in a matrix of SiO2 [3] (other cases include SiN and SiC matrices).It is observed that the mechanical properties are the functions of the QD size, shape and strain rate as it is in the case for nanowires [2]. We also present the comparative study resulted from the application of different EAM potentials in particular, the Stillinger-Weber (SW) potential, the Tersoff potentials and the environment-dependent interatomic potential (EDIP) [1]. Finally, based on the stabilized structural properties we compute electronic bandstructures of our nanostructures using an envelope function approach and its finite element implementation.

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The focus of this paper is on designing useful compliant micro-mechanisms of high-aspect-ratio which can be microfabricated by the cost-effective wet etching of (110) orientation silicon (Si) wafers. Wet etching of (110) Si imposes constraints on the geometry of the realized mechanisms because it allows only etch-through in the form of slots parallel to the wafer's flat with a certain minimum length. In this paper, we incorporate this constraint in the topology optimization and obtain compliant designs that meet the specifications on the desired motion for given input forces. Using this design technique and wet etching, we show that we can realize high-aspect-ratio compliant micro-mechanisms. For a (110) Si wafer of 250 µm thickness, the minimum length of the etch opening to get a slot is found to be 866 µm. The minimum achievable width of the slot is limited by the resolution of the lithography process and this can be a very small value. This is studied by conducting trials with different mask layouts on a (110) Si wafer. These constraints are taken care of by using a suitable design parameterization rather than by imposing the constraints explicitly. Topology optimization, as is well known, gives designs using only the essential design specifications. In this work, we show that our technique also gives manufacturable mechanism designs along with lithography mask layouts. Some designs obtained are transferred to lithography masks and mechanisms are fabricated on (110) Si wafers.

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Silicon oxide films were deposited by reactive evaporation of SiO. Parameters such as oxygen partial pressure and substrate temperature were varied to get variable and graded index films. Films with a refractive index in the range 1.718 to 1.465 at 550 nm have been successfully deposited. Films deposited using ionized oxygen has the refractive index 1.465 at 550 nm and good UV transmittance like bulk fused quartz. Preparation of graded index films was also investigated by changing the oxygen partial pressure during deposition. A two layer antireflection coating at 1064nm has been designed using both homogeneous and inhomogeneous films and studied their characteristics.

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Nanowires of Pr0.57Ca0.41Ba0.02MnO3 (PCBM) (diameter similar to 80-90 nm and length similar to 3.5 mu m) were synthesized by a low reaction temperature hydrothermal method. Single-phase nature of the sample was confirmed by XRD experiments. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) were used to characterize the morphology and microstructures of the nanowires. While the bulk PCBM is known to exhibit charge order (CO) below 230 K along with a ferromagnetic transition at 110 K, SQUID measurements on the nanowires of PCBM show that the charge order is completely absent and a ferromagnetic transition occurs at 115 K. However, the magnetization in the nanowires is observed to be less compared to that in the bulk. This observation of the complete 'melting' of the charge order in the PCBM nanowires is particularly significant in view of the observation of only a weakening of the CO in the nanowires of Pr0.5Ca0.5MnO3. Electron paramagnetic resonance experiments were also carried out on the PCBM nanowires using an X-band EPR spectrometer. Characteristic differences were observed in the line width of nanowires when compared with that of the bulk.

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InN quantum dots (QDs) were fabricated on silicon nitride/Si (111) substrate by droplet epitaxy. Single-crystalline structure of InN QDs was verified by transmission electron microscopy, and the chemical bonding configurations of InN QDs were examined by x-ray photoelectron spectroscopy. Photoluminescence measurement shows a slight blue shift compared to the bulk InN, arising from size dependent quantum confinement effect. The interdigitated electrode pattern was created and current-voltage (I-V) characteristics of InN QDs were studied in a metal-semiconductor-metal configuration in the temperature range of 80-300K. The I-V characteristics of lateral grown InN QDs were explained by using the trap model. (C) 2011 American Institute of Physics. [doi:10.1063/1.3651762]

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Continuous advances in VLSI technology have made implementation of very complicated systems possible. Modern System-on -Chips (SoCs) have many processors, IP cores and other functional units. As a result, complete verification of whole systems before implementation is becoming infeasible; hence it is likely that these systems may have some errors after manufacturing. This increases the need to find design errors in chips after fabrication. The main challenge for post-silicon debug is the observability of the internal signals. Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall verification effort on large designs, and the problem is growing worse.Traditional post-silicon debug methods concentrate on functional parts of systems and provide mechanisms to increase the observability of internal state of systems. Those methods may not be sufficient as modern SoCs have lots of blocks (processors, IP cores, etc.) which are communicating with one another and communication is another source of design errors. This tutorial will be provide an insight into various observability enhancement techniques, on chip instrumentation techniques and use of high level models to support the debug process targeting both inside blocks and communication among them. It will also cover the use of formal methods to help debug process.