Study of texture evolution of Pure Magnesium during ECAE using EBSD

Commercially Pure Magnesium initially hot rolled and having a basal texture was deformed by Equal Channel Angular Extrusion (ECAE). ECAE was carried out upto 8 passes in a 90° die following routes A and Bc through a processing sequence involving two temperatures, namely 523 and 473 K. Texture and microstructure formed were studied using electron back scatter diffraction (EBSD) technique. In addition to significant reduction in grain size, strong <0002> fiber texture inclined at an angle ~ 45o from the extrusion axis formed in the material. Texture was also analyzed by orientation distribution function (ODF) and compared vis-à-vis shear texture. A significant amount of dynamic recrystallization occurred during ECAE, which apparently did not influence texture.

Displacement Amplifying Compliant Mechanisms for Two-axis High-resolution Monolithic Inertial Sensors

Novel designs for two-axis, high-resolution, monolithic inertial sensors are presented in this paper. Monolithic, i.e., joint-less single-piece compliant designs are already common in micromachined inertial sensors such as accelerometers and gyroscopes. Here, compliant mechanisms are used not only to achieve de-coupling between motions along two orthogonal axes but also to amplify the displacements of the proof-mass. Sensitivity and resolution capabilities are enhanced because the amplified motion is used for sensing the measurand. A particular symmetric arrangement of displacement-amplifying compliant mechanisms (DaCMs) leads to de-coupled and amplified motion. An existing DaCM and a new topology-optimized DaCM are presented as a building block in the new arrangement. A spring-mass-lever model is presented as a lumped abstraction of the new arrangement. This model is useful for arriving at the optimal parameters of the DaCM and for performing system-level simulation. The new designs improved the performance by a factor of two or more.

Topology Optimization of Micromachined Structures with the Manufacturing Constraints of KOH Etching of (110) Silicon

The focus of this paper is on designing useful compliant micro-mechanisms of high-aspect-ratio which can be microfabricated by the cost-effective wet etching of (110) orientation silicon (Si) wafers. Wet etching of (110) Si imposes constraints on the geometry of the realized mechanisms because it allows only etch-through in the form of slots parallel to the wafer's flat with a certain minimum length. In this paper, we incorporate this constraint in the topology optimization and obtain compliant designs that meet the specifications on the desired motion for given input forces. Using this design technique and wet etching, we show that we can realize high-aspect-ratio compliant micro-mechanisms. For a (110) Si wafer of 250 µm thickness, the minimum length of the etch opening to get a slot is found to be 866 µm. The minimum achievable width of the slot is limited by the resolution of the lithography process and this can be a very small value. This is studied by conducting trials with different mask layouts on a (110) Si wafer. These constraints are taken care of by using a suitable design parameterization rather than by imposing the constraints explicitly. Topology optimization, as is well known, gives designs using only the essential design specifications. In this work, we show that our technique also gives manufacturable mechanism designs along with lithography mask layouts. Some designs obtained are transferred to lithography masks and mechanisms are fabricated on (110) Si wafers.

A Comparative Study of the Formulations for Topology Optimization of Compliant Mechanisms

The topology optimization problem for the synthesis of compliant mechanisms has been formulated in many different ways in the last 15 years, but there is not yet a definitive formulation that is universally accepted. Furthermore, there are two unresolved issues in this problem. In this paper, we present a comparative study of five distinctly different formulations that are reported in the literature. Three benchmark examples are solved with these formulations using the same input and output specifications and the same numerical optimization algorithm. A total of 35 different synthesis examples are implemented. The examples are limited to desired instantaneous output direction for prescribed input force direction. Hence, this study is limited to linear elastic modeling with small deformations. Two design parameterizations, namely, the frame element based ground structure and the density approach using continuum elements, are used. The obtained designs are evaluated with all other objective functions and are compared with each other. The checkerboard patterns, point flexures, the ability to converge from an unbiased uniform initial guess, and the computation time are analyzed. Some observations are noted based on the extensive implementation done in this study. Complete details of the benchmark problems and the results are included. The computer codes related to this study are made available on the internet for ready access.

Region Based Structure Layout Optimization by Selective Data Copying

As the gap between processor and memory continues to grow Memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to modify an application’s data layout to improve cache locality and cache reuse. Whole program Structure Layout [WPSL] transformations can significantly increase the spatial locality of data and reduce the runtime of programs that use link-based data structures, by increasing the cache line utilization. However, in production compilers WPSL transformations do not realize the entire performance potential possible due to a number of factors. Structure layout decisions made on the basis of whole program aggregated affinity/hotness of structure fields, can be sub optimal for local code regions. WPSL is also restricted in applicability in production compilers for type unsafe languages like C/C++ due to the extensive legality checks and field sensitive pointer analysis required over the entire application. In order to overcome the issues associated with WPSL, we propose Region Based Structure Layout (RBSL) optimization framework, using selective data copying. We describe our RBSL framework, implemented in the production compiler for C/C++ on HP-UX IA-64. We show that acting in complement to the existing and mature WPSL transformation framework in our compiler, RBSL improves application performance in pointer intensive SPEC benchmarks ranging from 3% to 28% over WPSL

Microwave spectrum and structure of C(6)H(5)CCH center dot center dot center dot H(2)S complex

Rotational spectra of C(6)H(5)CCH center dot center dot center dot H(2)S, C(6)H(5)CCH center dot center dot center dot H(2)(34)S, C(6)H(5)CCH center dot center dot center dot HDS, C(6)H(5)CCH center dot center dot center dot D(2)S and C(6) H(5)CCD center dot center dot center dot H(2)S complexes have been observed using a pulsed nozzle Fourier transform microwave spectrometer. The observed spectrum is consistent with a structure in which hydrogen sulfide is located over the phenyl ring pi cloud and the distance between the centers of masses of the two monomers is 3.74 +/- 0.01 angstrom. In the complex, the H(2)S unit is shifted from the phenyl ring center towards the acetylene group. The vibrationally averaged structure has an effective Cs symmetry. Ab initio calculations were performed at MP2/aug-cc-pVDZ level of theory to locate the possible geometries of the complex. The calculations reveal the experimentally observed structure to be more stable than a coplanar arrangement of the monomers, which was observed for the C(6)H(5)CCH center dot center dot center dot H(2)O complex. Atoms in molecule theoretical analysis shows the presence of S-H center dot center dot center dot pi hydrogen bond. For the parent isotopologue, each transition frequency was found to split into two resulting from an interchange of the equivalent hydrogens of H(2)S unit in the complex. (C) 2011 Elsevier Inc. All rights reserved.

STEM+: A Fair and Efficient Algorithm for Scheduling on the DSCH in UMTS Networks

In Universal Mobile Telecommunication Systems (UMTS), the Downlink Shared Channel (DSCH) can be used for providing streaming services. The traffic model for streaming services is different from the commonly used continuously- backlogged model. Each connection specifies a required service rate over an interval of time, k, called the "control horizon". In this paper, our objective is to determine how k DSCH frames should be shared among a set of I connections. We need a scheduler that is efficient and fair and introduce the notion of discrepancy to balance the conflicting requirements of aggregate throughput and fairness. Our motive is to schedule the mobiles in such a way that the schedule minimizes the discrepancy over the k frames. We propose an optimal and computationally efficient algorithm, called STEM+. The proof of the optimality of STEM+, when applied to the UMTS rate sets is the major contribution of this paper. We also show that STEM+ performs better in terms of both fairness and aggregate throughput compared to other scheduling algorithms. Thus, STEM+ achieves both fairness and efficiency and is therefore an appealing algorithm for scheduling streaming connections.

A fast algorithm for finding frequent episodes in event streams

Frequent episode discovery is a popular framework for mining data available as a long sequence of events. An episode is essentially a short ordered sequence of event types and the frequency of an episode is some suitable measure of how often the episode occurs in the data sequence. Recently,we proposed a new frequency measure for episodes based on the notion of non-overlapped occurrences of episodes in the event sequence, and showed that, such a definition, in addition to yielding computationally efficient algorithms, has some important theoretical properties in connecting frequent episode discovery with HMM learning. This paper presents some new algorithms for frequent episode discovery under this non-overlapped occurrences-based frequency definition. The algorithms presented here are better (by a factor of N, where N denotes the size of episodes being discovered) in terms of both time and space complexities when compared to existing methods for frequent episode discovery. We show through some simulation experiments, that our algorithms are very efficient. The new algorithms presented here have arguably the least possible orders of spaceand time complexities for the task of frequent episode discovery.

Estimation of missing data using windowed linear prediction in laterally truncated projection & in cone beam CT

In this paper, we address the reconstruction problem from laterally truncated helical cone-beam projections. The reconstruction problem from lateral truncation, though similar to that of interior radon problem, is slightly different from it as well as the local (lambda) tomography and pseudo-local tomography in the sense that we aim to reconstruct the entire object being scanned from a region-of-interest (ROI) scan data. The method proposed in this paper is a projection data completion approach followed by the use of any standard accurate FBP type reconstruction algorithm. In particular, we explore a windowed linear prediction (WLP) approach for data completion and compare the quality of reconstruction with the linear prediction (LP) technique proposed earlier.

REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures

In this paper we propose the architecture of a SoC fabric onto which applications described in a HLL are synthesized. The fabric is a homogeneous layout of computation, storage and communication resources on silicon. Through a process of composition of resources (as opposed to decomposition of applications), application specific computational structures are defined on the fabric at runtime to realize different modules of the applications in hardware. Applications synthesized on this fabric offers performance comparable to ASICs while retaining the programmability of processing cores. We outline the application synthesis methodology through examples, and compare our results with software implementations on traditional platforms with unbounded resources.