Cognitive radio implementation for a frequency hopping primary signal

Frequency hopping communications, used in the military present significant opportunities for spectrum reuse via the cognitive radio technology. We propose a MAC which incorporates hop instant identification, and supports network discovery and formation, QOS Scheduling and secondary communications. The spectrum sensing algorithm is optimized to deal with the problem of spectral leakage. The algorithms are implemented in a SDR platform based test bed and measurement results are presented.

Simulation of inhomogeneous distributions of ultracold atoms in an optical lattice via a massively parallel implementation of nonequilibrium strong-coupling perturbation theory

We present a nonequilibrium strong-coupling approach to inhomogeneous systems of ultracold atoms in optical lattices. We demonstrate its application to the Mott-insulating phase of a two-dimensional Fermi-Hubbard model in the presence of a trap potential. Since the theory is formulated self-consistently, the numerical implementation relies on a massively parallel evaluation of the self-energy and the Green's function at each lattice site, employing thousands of CPUs. While the computation of the self-energy is straightforward to parallelize, the evaluation of the Green's function requires the inversion of a large sparse 10(d) x 10(d) matrix, with d > 6. As a crucial ingredient, our solution heavily relies on the smallness of the hopping as compared to the interaction strength and yields a widely scalable realization of a rapidly converging iterative algorithm which evaluates all elements of the Green's function. Results are validated by comparing with the homogeneous case via the local-density approximation. These calculations also show that the local-density approximation is valid in nonequilibrium setups without mass transport.

Nearly Constant Switching Frequency Hysteresis Current Controller with Fast Online Computation of Boundary for a 2-Level Induction Motor Drive

A nearly constant switching frequency current hysteresis controller for a 2-level inverter fed induction motor drive is proposed in this paper: The salient features of this controller are fast dynamics for the current, inherent protection against overloads and less switching frequency variation. The large variation of switching frequency as in the conventional hysteresis controller is avoided by defining a current-error boundary which is obtained from the current-error trajectory of the standard space vector PWM. The current-error boundary is computed at every sampling interval based on the induction machine parameters and from the estimated fundamental stator voltage. The stator currents are always monitored and when the current-error exceeds the boundary, voltage space vector is switched to reduce the current-error. The proposed boundary computation algorithm is applicable in linear and over-modulation region and it is simple to implement in any standard digital signal processor: Detailed experimental verification is done using a 7.5 kW induction motor and the results are given to show the performance of the drive at various operating conditions and validate the proposed advantages.

Modeling Equitable Distribution of Water: Dynamic Inversion-Based Controller Approach

It is a well-known fact that most of the developing countries have intermittent water supply and the quantity of water supplied from the source is also not distributed equitably among the consumers. Aged pipelines, pump failures, and improper management of water resources are some of the main reasons for it. This study presents the application of a nonlinear control technique to overcome this problem in different zones in the city of Bangalore. The water is pumped to the city from a large distance of approximately 100km over a very high elevation of approximately 400m. The city has large undulating terrain among different zones, which leads to unequal distribution of water. The Bangalore, inflow water-distribution system (WDS) has been modeled. A dynamic inversion (DI) nonlinear controller with proportional integral derivative (PID) features (DI-PID) is used for valve throttling to achieve the target flows to different zones of the city. This novel approach of equitable water distribution using DI-PID controllers that can be used as a decision support system is discussed in this paper.

Hysteresis current controller for a general n-level inverter fed drive with online current error boundary computation and nearly constant switching frequency

A space vector-based hysteresis current controller for any general n-level three phase inverter fed induction motor drive is proposed in this study. It offers fast dynamics, inherent overload protection and low harmonic distortion for the phase voltages and currents. The controller performs online current error boundary calculations and a nearly constant switching frequency is obtained throughout the linear modulation range. The proposed scheme uses only the adjacent voltage vectors of the present sector, similar to space vector pulse-width modulation and exhibits fast dynamic behaviour under different transient conditions. The steps involved in the boundary calculation include the estimation of phase voltages from the current ripple, computation of switching time and voltage error vectors. Experimental results are given to show the performance of the drive at various speeds, effect of sudden change of the load, acceleration, speed reversal and validate the proposed advantages.

A fractional order proportional integral controller for path following and trajectory tracking of miniature air vehicles

In this paper, a fractional order proportional-integral controller is developed for a miniature air vehicle for rectilinear path following and trajectory tracking. The controller is implemented by constructing a vector field surrounding the path to be followed, which is then used to generate course commands for the miniature air vehicle. The fractional order proportional-integral controller is simulated using the fundamentals of fractional calculus, and the results for this controller are compared with those obtained for a proportional controller and a proportional integral controller. In order to analyze the performance of the controllers, four performance metrics, namely (maximum) overshoot, control effort, settling time and integral of the timed absolute error cost, have been selected. A comparison of the nominal as well as the robust performances of these controllers indicates that the fractional order proportional-integral controller exhibits the best performance in terms of ITAE while showing comparable performances in all other aspects.

Toward a Scalable Working Set Size Estimation Method and Its Application for Chip Multiprocessors

It is essential to accurately estimate the working set size (WSS) of an application for various optimizations such as to partition cache among virtual machines or reduce leakage power dissipated in an over-allocated cache by switching it OFF. However, the state-of-the-art heuristics such as average memory access latency (AMAL) or cache miss ratio (CMR) are poorly correlated to the WSS of an application due to 1) over-sized caches and 2) their dispersed nature. Past studies focus on estimating WSS of an application executing on a uniprocessor platform. Estimating the same for a chip multiprocessor (CMP) with a large dispersed cache is challenging due to the presence of concurrently executing threads/processes. Hence, we propose a scalable, highly accurate method to estimate WSS of an application. We call this method ``tagged WSS (TWSS)'' estimation method. We demonstrate the use of TWSS to switch-OFF the over-allocated cache ways in Static and Dynamic NonUniform Cache Architectures (SNUCA, DNUCA) on a tiled CMP. In our implementation of adaptable way SNUCA and DNUCA caches, decision of altering associativity is taken by each L2 controller. Hence, this approach scales better with the number of cores present on a CMP. It gives overall (geometric mean) 26% and 19% higher energy-delay product savings compared to AMAL and CMR heuristics on SNUCA, respectively.

An Implementation of Partitioned Scheduling Scheme for Hard Real-Time Tasks in Multicore Linux with Fair Share for Linux Tasks

The correctness of a hard real-time system depends its ability to meet all its deadlines. Existing real-time systems use either a pure real-time scheduler or a real-time scheduler embedded as a real-time scheduling class in the scheduler of an operating system (OS). Existing implementations of schedulers in multicore systems that support real-time and non-real-time tasks, permit the execution of non-real-time tasks in all the cores with priorities lower than those of real-time tasks, but interrupts and softirqs associated with these non-real-time tasks can execute in any core with priorities higher than those of real-time tasks. As a result, the execution overhead of real-time tasks is quite large in these systems, which, in turn, affects their runtime. In order that the hard real-time tasks can be executed in such systems with minimal interference from other Linux tasks, we propose, in this paper, an integrated scheduler architecture, called SchedISA, which aims to considerably reduce the execution overhead of real-time tasks in these systems. In order to test the efficacy of the proposed scheduler, we implemented partitioned earliest deadline first (P-EDF) scheduling algorithm in SchedISA on Linux kernel, version 3.8, and conducted experiments on Intel core i7 processor with eight logical cores. We compared the execution overhead of real-time tasks in the above implementation of SchedISA with that in SCHED_DEADLINE's P-EDF implementation, which concurrently executes real-time and non-real-time tasks in Linux OS in all the cores. The experimental results show that the execution overhead of real-time tasks in the above implementation of SchedISA is considerably less than that in SCHED_DEADLINE. We believe that, with further refinement of SchedISA, the execution overhead of real-time tasks in SchedISA can be reduced to a predictable maximum, making it suitable for scheduling hard real-time tasks without affecting the CPU share of Linux tasks.

Experimental results on low cost microcontroller based DC drive implementation

This paper presents the experimental results for an attractive control scheme implementation using an 8 bit microcontroller. The power converter involved is a 3 phase full controlled bridge rectifier. A single quadrant DC drive has been realized and results have been presented for both open and closed loop implementations.

Soft Real Time Implementation of a Cognitive Radio Testbed for Frequency Hopping Primary Satisfying QoS Requirements

The Cognitive Radio (CR) is a promising technology which provides a novel way to subjugate the issue of spectrum underutilization caused due to the fixed spectrum assignment policies. In this paper we report the design and implementation of a soft-real time CR MAC, consisting of multiple secondary users, in a frequency hopping (Fit) primary scenario. This MAC is capable of sensing the spectrum and dynamically allocating the available frequency bands to multiple CR users based on their QoS requirements. As the primary is continuously hopping, a method has also been implemented to detect the hop instant of the primary network. Synchronization usually requires real time support, however we have been able to achieve this with a soft-real time technique which enables a fully software implementation of CR MAC layer. We demonstrate the wireless transmission and reception of video over this CR testbed through opportunistic spectrum access. The experiments carried out use an open source software defined radio package called GNU Radio and a basic radio hardware component USRP.

ANRC Hybrid Test Bed Implementation and an End-to-End Performance Characterization of Dynamic Spectrum Access

An abundance of spectrum access and sensing algorithms are available in the dynamic spectrum access (DSA) and cognitive radio (CR) literature. Often, however, the functionality and performance of such algorithms are validated against theoretical calculations using only simulations. Both the theoretical calculations and simulations come with their attendant sets of assumptions. For instance, designers of dynamic spectrum access algorithms often take spectrum sensing and rendezvous mechanisms between transmitter-receiver pairs for granted. Test bed designers, on the other hand, either customize so much of their design that it becomes difficult to replicate using commercial off the shelf (COTS) components or restrict themselves to simulation, emulation /hardware-in-Ioop (HIL), or pure hardware but not all three. Implementation studies on test beds sophisticated enough to combine the three aforementioned aspects, but at the same time can also be put together using COTS hardware and software packages are rare. In this paper we describe i) the implementation of a hybrid test bed using a previously proposed hardware agnostic system architecture ii) the implementation of DSA on this test bed, and iii) the realistic hardware and software-constrained performance of DSA. Snapshot energy detector (ED) and Cumulative Summation (CUSUM), a sequential change detection algorithm, are available for spectrum sensing and a two-way handshake mechanism in a dedicated control channel facilitates transmitter-receiver rendezvous.

Flexible implementation of power system corrective topology control

This paper proposes a novel decision making framework for optimal transmission switching satisfying the AC feasibility, stability and circuit breaker (CB) reliability requirements needed for practical implementation. The proposed framework can be employed as a corrective tool in day to day operation planning scenarios in response to potential contingencies. The switching options are determined using an efficient heuristic algorithm based on DC optimal power flow, and are presented in a multi-branch tree structure. Then, the AC feasibility and stability checks are conducted and the CB condition monitoring data are employed to perform a CB reliability and line availability assessment. Ultimately, the operator will be offered multiple AC feasible and stable switching options with associated benefits. The operator can use this information, other operating conditions not explicitly considered in the optimization, and his/her own experience to implement the best and most reliable switching action(s). The effectiveness of the proposed approach is validated on the IEEE-118 bus test system. (C) 2015 Elsevier B.V. All rights reserved.

A controller design method for 3 phase 4 wire grid connected VSI with LCL filter

Closed loop control of a grid connected VSI requires line current control and dc bus voltage control. The closed loop system comprising PR current controller and grid connected VSI with LCL filter is a higher order system. Closed loop control gain expressions are therefore difficult to obtain directly for such systems. In this work a simplified approach has been adopted to find current and voltage controller gain expressions for a 3 phase 4 wire grid connected VSI with LCL filter. The closed loop system considered here utilises PR current controller in natural reference frame and PI controller for dc bus voltage control. Asymptotic frequency response plot and gain bandwidth requirements of the system have been used for current control and voltage controller design. A simplified lower order model, derived for closed loop current control, is used for the dc bus voltage controller design. The adopted design method has been verified through experiments by comparison of the time domain response.

Design and implementation of spectrum sensing for cognitive radios with a frequency-hopping primary system

In this work, spectrum sensing for cognitive radios is considered in the presence of multiple Primary Users (PU) using frequency-hopping communication over a set of frequency bands. The detection performance of the Fast Fourier Transform (FFT) Average Ratio (FAR) algorithm is obtained in closed-form, for a given FFT size and number of PUs. The effective throughput of the Secondary Users (SU) is formulated as an optimization problem with a constraint on the maximum allowable interference on the primary network. Given the hopping period of the PUs, the sensing duration that maximizes the SU throughput is derived. The results are validated using Monte Carlo simulations. Further, an implementation of the FAR algorithm on the Lyrtech (now, Nutaq) small form factor software defined radio development platform is presented, and the performance recorded through the hardware is observed to corroborate well with that obtained through simulations, allowing for implementation losses. (C) 2015 Elsevier B.V. All rights reserved.