Register Allocation and Optimal Spill code Scheduling in Software Pipelined Loops using 0-1 Integer Linear Programming Formulation

In achieving higher instruction level parallelism, software pipelining increases the register pressure in the loop. The usefulness of the generated schedule may be restricted to cases where the register pressure is less than the available number of registers. Spill instructions need to be introduced otherwise. But scheduling these spill instructions in the compact schedule is a difficult task. Several heuristics have been proposed to schedule spill code. These heuristics may generate more spill code than necessary, and scheduling them may necessitate increasing the initiation interval. We model the problem of register allocation with spill code generation and scheduling in software pipelined loops as a 0-1 integer linear program. The formulation minimizes the increase in initiation interval (II) by optimally placing spill code and simultaneously minimizes the amount of spill code produced. To the best of our knowledge, this is the first integrated formulation for register allocation, optimal spill code generation and scheduling for software pipelined loops. The proposed formulation performs better than the existing heuristics by preventing an increase in II in 11.11% of the loops and generating 18.48% less spill code on average among the loops extracted from Perfect Club and SPEC benchmarks with a moderate increase in compilation time.

Training-Symbol Embedded, High-Rate, Single-Symbol ML-Decodable, Distributed STBCs for Relay Networks

Distributed space-time block codes (DSTBCs) from complex orthogonal designs (CODs) (both square and nonsquare), coordinate interleaved orthogonal designs (CIODs), and Clifford unitary weight designs (CUWDs) are known to lose their single-symbol ML decodable (SSD) property when used in two-hop wireless relay networks using amplify and forward protocol. For such networks, in this paper, three new classes of high rate, training-symbol embedded (TSE) SSD DSTBCs are constructed: TSE-CODs, TSE-CIODs, and TSE-CUWDs. The proposed codes include the training symbols inside the structure of the code which is shown to be the key point to obtain the SSD property along with the channel estimation capability. TSE-CODs are shown to offer full-diversity for arbitrary complex constellations and the constellations for which TSE-CIODs and TSE-CUWDs offer full-diversity are characterized. It is shown that DSTBCs from nonsquare TSE-CODs provide better rates (in symbols per channel use) when compared to the known SSD DSTBCs for relay networks. Important from the practical point of view, the proposed DSTBCs do not contain any zeros in their codewords and as a result, antennas of the relay nodes do not undergo a sequence of switch on/off transitions within every codeword, and, thus, avoid the antenna switching problem.

Novel Switching Sequences for a Space-Vector-Modulated Three-Level Inverter

A three-level inverter produces six active vectors, each of normalized magnitudes 1, 0.866, and 0.5, besides a zero vector. The vectors of relative length 0.5 are termed pivot vectors.The three nearest voltage vectors are usually used to synthesize the reference vector. In most continuous pulsewidth-modulation(PWM) schemes, the switching sequence begins from a pivot vector and ends with the same pivot vector. Thus, the pivot vector is applied twice in a subcycle or half-carrier cycle. This paper proposes and investigates alternative switching sequences, which use the pivot vector only once but employ one of the other two vectors twice within the subcycle. The total harmonic distortion(THD) in the fundamental line current pertaining to these novel sequences is studied theoretically as well as experimentally over the whole range of modulation. Compared with centered space vector PWM, two of the proposed sequences lead to reduced THD at high modulation indices at a given average switching frequency.

Collocated and Distributed STBCs with Partial Interference Cancellation Decoding, Part II: Code Construction

In this second part of a two part series of papers, we construct a new class of Space-Time Block Codes (STBCs) for point-to-point MIMO channel and Distributed STBCs (DSTBCs) for the amplify-and-forward relay channel that give full-diversity with Partial Interference Cancellation (PIC) and PIC with Successive Interference Cancellation (PIC-SIC) decoders. The proposed class of STBCs include most of the known full-diversity low complexity PIC/PIC-SIC decodable STBCs as special cases. We also show that a number of known full-diversity PIC/PIC-SIC decodable STBCs that were constructed for the point-topoint MIMO channel can be used as full-diversity PIC/PIC-SIC decodable DSTBCs in relay networks. For the same decoding complexity, the proposed STBCs and DSTBCs achieve higher rates than the known low decoding complexity codes. Simulation results show that the new codes have a better bit error rate performance than the low ML decoding complexity codes available in the literature.

Improving Superscalar Instruction Dispatch And Issue By Exploiting Dynamic Code Sequences

Superscalar processors currently have the potential to fetch multiple basic blocks per cycle by employing one of several recently proposed instruction fetch mechanisms. However, this increased fetch bandwidth cannot be exploited unless pipeline stages further downstream correspondingly improve. In particular,register renaming a large number of instructions per cycle is diDcult. A large instruction window, needed to receive multiple basic blocks per cycle, will slow down dependence resolution and instruction issue. This paper addresses these and related issues by proposing (i) partitioning of the instruction window into multiple blocks, each holding a dynamic code sequence; (ii) logical partitioning of the registerjle into a global file and several local jles, the latter holding registers local to a dynamic code sequence; (iii) the dynamic recording and reuse of register renaming information for registers local to a dynamic code sequence. Performance studies show these mechanisms improve performance over traditional superscalar processors by factors ranging from 1.5 to a little over 3 for the SPEC Integer programs. Next, it is observed that several of the loops in the benchmarks display vector-like behavior during execution, even if the static loop bodies are likely complex for compile-time vectorization. A dynamic loop vectorization mechanism that builds on top of the above mechanisms is briefly outlined. The mechanism vectorizes up to 60% of the dynamic instructions for some programs, albeit the average number of iterations per loop is quite small.

Backward switching phenomenon from field forced ferroelectric to antiferroelectric phases in antiferroelectric PbZrO3 thin films

Antiferroelectric materials (example: lead zirconate and modified lead zirconate stannate), in which a field-induced ferroelectric phase transition is feasible due to a small free energy difference between the ferroelectric and the antiferroelectric phases, are proven to be very good candidates for applications involving actuation and high charge storage devices. The property of reverse switching from the field-induced ferroelectric to antiferroelectric phases is studied as a function of temperature, applied electric field, and sample thickness in antiferroelectric lead zirconate thin films deposited by pulsed excimer laser ablation. The maximum released charge density was 22 μC/cm2 from a stored charge density of 36 μC/cm2 in a 0.55 μ thick lead zirconate thin film. This indicated that more than 60% of the stored charge could be released in less than 7 ns at room temperature for a field of 200 kV/cm. The content of net released charge was found to increase with increasing field strength, whereas with increasing temperature the released charge was found to decrease. Thickness-dependent studies on lead zirconate thin films showed that size effects relating to extrinsic and intrinsic pinning mechanisms controlled the released and induced charges through the intrinsic switching time. These results proved that antiferroelectric PZ thin films could be utilized in high-speed charge decoupling capacitors in microelectronics applications.

High voltage DC power supply topology for pulsed load applications with converter switching synchronized to load pulses

High voltage power supplies for radar applications are investigated, which are subjected to pulsed load (125 kHz and 10% duty cycle) with stringent specifications (<0.01% regulation, efficiency>85%, droop<0.5 V/micro-sec.). As good regulation and stable operation requires the converter to be switched at much higher frequency than the pulse load frequency, transformer poses serious problems of insulation failure and higher losses. This paper proposes a methodology to tackle the problems associated with this type of application. Synchronization of converter switching with load pulses enables the converter to switch at half the load switching frequency. Low switching frequency helps in ensuring safety of HV transformer insulation and reduction of losses due to skin and proximity effect. Phase-modulated series resonant converter with ZVS is used as the power converter.

Thermodynamic, kinetic and electrical switching studies on Si(15)Te(85-x)In(x) glasses: Observation of Boolchand intermediate phase

An interesting topic for quite some time is an intermediate phase observed in chalcogenide glasses, which is related to network connectivity and rigidity. This phenomenon is exhibited by Si-Te-In glasses also. It has been addressed here by carrying out detailed thermal investigations by using Alternating Differential Scanning Calorimetry technique. An effort has also been made to determine the stability of these glasses using the data obtained from different thermodynamic quantities and crystallization kinetics of these glasses. Electrical switching behavior by recording I-V characteristics and variation of switching voltages with indium composition have been studied in these glasses for phase change memory applications. (C) 2011 Elsevier Inc. All rights reserved.

Colossal electroresistance and current induced switching in ferromagnetic insulating state of La0.82Ca0.18MnO3

Colossal electroresistance and current induced resistivity switching have been measured in the ferromagnetic insulating (FMI) state of single crystal manganite La0.82Ca0.18MnO3. The sample has a Curie transition temperature TC = 165 K and the FMI state is realized for temperatures T<100 K. The electroresistance (ER), arising from a strong nonlinear resistivity, attains a large value ( ≈ 100%) in the FMI state. However, this is accompanied by a collapse of the magnetoresistance (MR) to a small value even in magnetic field (H) of 10 T. This demonstrates that the mechanisms that give rise to ER and MR are effectively decoupled.

Switching Transients in Single-Phase Induction Motors

The subject of transients in polyphase induction motors and synchronous machines has been studied in very great detail by several investigators, but no published literature exists dealing exclusively with the analysis of the problem of transients in single-phase induction motors. This particular problem has been studied in this paper by applying the Laplace transform. The results of actual computation of the currents and developed electrical torque are compared with the data obtained by setting up the integro-differential equations of the machine on an electronic differential analyzer. It is shown that if the motor is switched on to the supply when the potential passes through its zero value, there is a pulsating fundamental frequency torque superimposed on the average steady-state unidirectional torque. If, on the other hand, the switch is closed when the applied potential passes through its maximum value, the developed electrical torque settles down to its final steady-state value during the first cycle of the supply voltage.