Genetic diversity and proviral DNA load in different neural compartments of HIV-1 subtype C infection

In India, the low prevalence of HIV-associated dementia (HAD) in the Human immunodeficiency virus type 1 (HIV-1) subtype C infection is quite paradoxical given the high-rate of macrophage infiltration into the brain. Whether the direct viral burden in individual brain compartments could be associated with the variability of the neurologic manifestations is controversial. To understand this paradox, we examined the proviral DNA load in nine different brain regions and three different peripheral tissues derived from ten human subjects at autopsy. Using a highly sensitive TaqMan probe-based real-time PCR, we determined the proviral load in multiple samples processed in parallel from each site. Unlike previously published reports, the present analysis identified uniform proviral distribution among the brain compartments examined without preferential accumulation of the DNA in any one of them. The overall viral DNA burden in the brain tissues was very low, approximately 1 viral integration per 1000 cells or less. In a subset of the tissue samples tested, the HIV DNA mostly existed in a free unintegrated form. The V3-V5 envelope sequences, demonstrated a brain-specific compartmentalization in four of the ten subjects and a phylogenetic overlap between the neural and non-neural compartments in three other subjects. The envelope sequences phylogenetically belonged to subtype C and the majority of them were R5 tropic. To the best of our knowledge, the present study represents the first analysis of the proviral burden in subtype C postmortem human brain tissues. Future studies should determine the presence of the viral antigens, the viral transcripts, and the proviral DNA, in parallel, in different brain compartments to shed more light on the significance of the viral burden on neurologic consequences of HIV infection.

Investigation of schemes for incorporating generator Q limits in the fast decoupled load flow method

Fast Decoupled Load Flow (FDLF) is a very popular and widely used power flow analysis method because of its simplicity and efficiency. Even though the basic FDLF algorithm is well investigated, the same is not true in the case of additional schemes/modifications required to obtain adjusted load flow solutions using the FDLF method. Handling generator Q limits is one such important feature needed in any practical load flow method. This paper presents a comprehensive investigation of two classes of schemes intended to handle this aspect i.e. the bus type switching scheme and the sensitivity scheme. We propose two new sensitivity based schemes and assess their performance in comparison with the existing schemes. In addition, a new scheme to avoid the possibility of anomalous solutions encountered while using the conventional schemes is also proposed and evaluated. Results from extensive simulation studies are provided to highlight the strengths and weaknesses of these existing and proposed schemes, especially from the point of view of reliability.

Load Balancing with Availability Checker and Load Reporters (LB-ACLRs) for improved Performance in Distributed Systems

Distributed system has quite a lot of servers to attain increased availability of service and for fault tolerance. Balancing the load among these servers is an important task to achieve better performance. There are various hardware and software based load balancing solutions available. However there is always an overhead on Servers and the Load Balancer while communicating with each other and sharing their availability and the current load status information. Load balancer is always busy in listening to clients' request and redirecting them. It also needs to collect the servers' availability status frequently, to keep itself up-to-date. Servers are busy in not only providing service to clients but also sharing their current load information with load balancing algorithms. In this paper we have proposed and discussed the concept and system model for software based load balancer along with Availability-Checker and Load Reporters (LB-ACLRs) which reduces the overhead on server and the load balancer. We have also described the architectural components with their roles and responsibilities. We have presented a detailed analysis to show how our proposed Availability Checker significantly increases the performance of the system.

A Simple Hysteretic Energy Harvesting Method for Nonneutral AC Switches in Load Automation

This paper presents a simple hysteretic method to obtain the energy required to operate the gate-drive, sensors, and other circuits within nonneutral ac switches intended for use in load automated buildings. The proposed method features a switch-mode low part-count self-powered MOSFET ac switch that achieves efficiency and load current THD figures comparable to those of an externally gate-driven switch built using similar MOSFETS. The fundamental operation of the method is explained in detail, followed by the modifications required for practical implementation. Certain design rules that allow the method to accommodate a wide range of single-phase loads from 10 VA to 1 kVA are discussed, along with an efficiency enhancement feature based on inherent MOSFET characteristics. The limitations and side effects of the method are also mentioned according to their levels of severity. Finally, experimental results obtained using a prototype sensor switch are presented, along with a performance comparison of the prototype with an externally gate-driven MOSFET switch.