Injection barrier induced deviations in space charge limited conduction in doped poly(3-methylthiophene) based devices

The carrier density dependent current-voltage (J V) characteristics of electrochemically prepared poly(3-methylthiophene) (P3MeT) have been investigated in Pt/P3MeT/Al devices, as a function of temperature from 280 to 84 K. In these devices, the charge transport is found to be mainly governed by different transport regimes of space charge limited conduction (SCLC). In a lightly doped device, SCLC controlled by exponentially distributed traps (Vl+1 law, l > 1) is observed in the intermediate voltage range (0.5-2 V) at all temperatures. However, at higher bias (> 2 V), the current deviates from the usual Vl+1 law where the slope is found to be less than 2 of the logJ-logV plot, which is attributed to the presence of the injection barrier. These deviations gradually disappear at higher doping level due to reduction in the injection barrier. Numerical simulations of the Vl+1 law by introducing the injection barrier show good agreement with experimental data. The results show that carrier density can tune the charge transport mechanism in Pt/P3MeT/Al devices to understand the non-Ohmic behavior. The plausible reasons for the origin of injection barrier and the transitions in the transport mechanism with carrier density are discussed. (C) 2015 AIP Publishing LLC.

DLTS analysis of amphoteric interface defects in high-TiO2 MOS structures prepared by sol-gel spin-coating

High-kappa TiO2 thin films have been fabricated from a facile, combined sol-gel spin - coating technique on p and n type silicon substrate. XRD and Raman studies headed the existence of anatase phase of TiO2 with a small grain size of 18 nm. The refractive index `n' quantified from ellipsometry is 2.41. AFM studies suggest a high quality, pore free films with a fairly small surface roughness of 6 angstrom. The presence of Ti in its tetravalent state is confirmed by XPS analysis. The defect parameters observed at the interface of Si/TiO2 were studied by capacitance - voltage (C - V) and deep level transient spectroscopy (DLTS). The flat - band voltage (V-FB) and the density of slow interface states estimated are -0.9, -0.44 V and 5.24x10(10), 1.03x10(11) cm(-2); for the NMOS and PMOS capacitors, respectively. The activation energies, interface state densities and capture cross -sections measured by DLTS are E-V + 0.30, E-C - 0.21 eV; 8.73x10(11), 6.41x10(11) eV(-1) cm(-2) and 5.8x10(-23), 8.11x10(-23) cm(2) for the NMOS and PMOS structures, respectively. A low value of interface state density in both P-and N-MOS structures makes it a suitable alternate dielectric layer for CMOS applications. And also very low value of capture cross section for both the carriers due to the amphoteric nature of defect indicates that the traps are not aggressive recombination centers and possibly can not contribute to the device operation to a large extent. (C) 2015 Author(s).

Tunability of 1/f Noise at Multiple Dirac Cones in hBN Encapsulated Graphene Devices

The emergence of multiple Dirac cones in hexagonal boron nitride (hBN)-graphene heterostructures is particularly attractive because it offers potentially better landscape for higher and versatile transport properties than the primary Dirac cone. However, the transport coefficients of the cloned Dirac cones is yet not fully characterized and many open questions, including the evolution of charge dynamics and impurity scattering responsible for them, have remained unexplored. Noise measurements, having the potential to address these questions, have not been performed to date in dual-gated hBN graphene hBN devices. Here, we present the low frequency 1/f noise measurements at multiple Dirac cones in hBN encapsulated single and bilayer graphene in dual-gated geometry. Our results reveal that the low-frequency noise in graphene can be tuned by more than two-orders of magnitude by changing carrier concentration as well as by modifying the band structure in bilayer graphene. We find that the noise is surprisingly suppressed at the cloned Dirac cone compared to the primary Dirac cone in single layer graphene device, while it is strongly enhanced for the bilayer graphene with band gap opening. The results are explained with the calculation of dielectric function using tight-binding model. Our results also indicate that the 1/f noise indeed follows the Hooge's empirical formula in hBN-protected devices in dual-gated geometry. We also present for the first time the noise data in bipolar regime of a graphene device.

All Inorganic Spin-Coated Nanoparticle-Based Capacitive Memory Devices

We demonstrate all inorganic, robust, cost-effective, spin-coated, two-terminal capacitive memory metal-oxide nanoparticle-oxide-semiconductor devices with cadmium telluride nanoparticles sandwiched between aluminum oxide phosphate layers to form the dielectric memory stack. Using a novel high-speed circuit to decouple reading and writing, experimentally measured memory windows, programming voltages, retention times, and endurance are comparable with or better than the two-terminal memory devices realized using other fabrication techniques.

On the Geometrically Dependent Quasi-Saturation and g(m) Reduction in Advanced DeMOS Transistors

This paper reveals an early quasi-saturation (QS) effect attributed to the geometrical parameters in shallow trench isolation-type drain-extended MOS (STI-DeMOS) transistors in advanced CMOS technologies. The quasi-saturation effect leads to serious g(m) reduction in STI-DeMOS. This paper investigates the nonlinear resistive behavior of the drain-extended region and its impact on the particular behavior of the STI-DeMOS transistor. In difference to vertical DMOS or lateral DMOS structures, STI-DeMOS exhibits three distinct regions of the drain extension. A complete understanding of the physics in these regions and their impact on the QS behavior are developed in this paper. An optimization strategy is shown for an improved g(m) device in a state-of-the-art 28-nm CMOS technology node.