140 resultados para Compliant parallel manipulator
Resumo:
Protein folding and unfolding are complex phenomena, and it is accepted that multidomain proteins generally follow multiple pathways. Maltose-binding protein (MBP) is a large (a two-domain, 370-amino acid residue) bacterial periplasmic protein involved in maltose uptake. Despite the large size, it has been shown to exhibit an apparent two-state equilibrium unfolding in bulk experiments. Single-molecule studies can uncover rare events that are masked by averaging in bulk studies. Here, we use single-molecule force spectroscopy to study the mechanical unfolding pathways of MBP and its precursor protein (preMBP) in the presence and absence of ligands. Our results show that MBP exhibits kinetic partitioning on mechanical stretching and unfolds via two parallel pathways: one of them involves a mechanically stable intermediate (path I) whereas the other is devoid of it (path II). The apoMBP unfolds via path I in 62% of the mechanical unfolding events, and the remaining 38% follow path II. In the case of maltose-bound MBP, the protein unfolds via the intermediate in 79% of the cases, the remaining 21% via path II. Similarly, on binding to maltotriose, a ligand whose binding strength with the polyprotein is similar to that of maltose, the occurrence of the intermediate is comparable (82% via path I) with that of maltose. The precursor protein preMBP also shows a similar behavior upon mechanical unfolding. The percentages of molecules unfolding via path I are 53% in the apo form and 68% and 72% upon binding to maltose and maltotriose, respectively, for preMBP. These observations demonstrate that ligand binding can modulate the mechanical unfolding pathways of proteins by a kinetic partitioning mechanism. This could be a general mechanism in the unfolding of other large two-domain ligand-binding proteins of the bacterial periplasmic space.
Resumo:
As computational Grids are increasingly used for executing long running multi-phase parallel applications, it is important to develop efficient rescheduling frameworks that adapt application execution in response to resource and application dynamics. In this paper, three strategies or algorithms have been developed for deciding when and where to reschedule parallel applications that execute on multi-cluster Grids. The algorithms derive rescheduling plans that consist of potential points in application execution for rescheduling and schedules of resources for application execution between two consecutive rescheduling points. Using large number of simulations, it is shown that the rescheduling plans developed by the algorithms can lead to large decrease in application execution times when compared to executions without rescheduling on dynamic Grid resources. The rescheduling plans generated by the algorithms are also shown to be competitive when compared to the near-optimal plans generated by brute-force methods. Of the algorithms, genetic algorithm yielded the most efficient rescheduling plans with 9-12% smaller average execution times than the other algorithms.
Resumo:
Novel designs for two-axis, high-resolution, monolithic inertial sensors are presented in this paper. Monolithic, i.e., joint-less single-piece compliant designs are already common in micromachined inertial sensors such as accelerometers and gyroscopes. Here, compliant mechanisms are used not only to achieve de-coupling between motions along two orthogonal axes but also to amplify the displacements of the proof-mass. Sensitivity and resolution capabilities are enhanced because the amplified motion is used for sensing the measurand. A particular symmetric arrangement of displacement-amplifying compliant mechanisms (DaCMs) leads to de-coupled and amplified motion. An existing DaCM and a new topology-optimized DaCM are presented as a building block in the new arrangement. A spring-mass-lever model is presented as a lumped abstraction of the new arrangement. This model is useful for arriving at the optimal parameters of the DaCM and for performing system-level simulation. The new designs improved the performance by a factor of two or more.
Resumo:
The focus of this paper is on designing useful compliant micro-mechanisms of high-aspect-ratio which can be microfabricated by the cost-effective wet etching of (110) orientation silicon (Si) wafers. Wet etching of (110) Si imposes constraints on the geometry of the realized mechanisms because it allows only etch-through in the form of slots parallel to the wafer's flat with a certain minimum length. In this paper, we incorporate this constraint in the topology optimization and obtain compliant designs that meet the specifications on the desired motion for given input forces. Using this design technique and wet etching, we show that we can realize high-aspect-ratio compliant micro-mechanisms. For a (110) Si wafer of 250 µm thickness, the minimum length of the etch opening to get a slot is found to be 866 µm. The minimum achievable width of the slot is limited by the resolution of the lithography process and this can be a very small value. This is studied by conducting trials with different mask layouts on a (110) Si wafer. These constraints are taken care of by using a suitable design parameterization rather than by imposing the constraints explicitly. Topology optimization, as is well known, gives designs using only the essential design specifications. In this work, we show that our technique also gives manufacturable mechanism designs along with lithography mask layouts. Some designs obtained are transferred to lithography masks and mechanisms are fabricated on (110) Si wafers.
Resumo:
The topology optimization problem for the synthesis of compliant mechanisms has been formulated in many different ways in the last 15 years, but there is not yet a definitive formulation that is universally accepted. Furthermore, there are two unresolved issues in this problem. In this paper, we present a comparative study of five distinctly different formulations that are reported in the literature. Three benchmark examples are solved with these formulations using the same input and output specifications and the same numerical optimization algorithm. A total of 35 different synthesis examples are implemented. The examples are limited to desired instantaneous output direction for prescribed input force direction. Hence, this study is limited to linear elastic modeling with small deformations. Two design parameterizations, namely, the frame element based ground structure and the density approach using continuum elements, are used. The obtained designs are evaluated with all other objective functions and are compared with each other. The checkerboard patterns, point flexures, the ability to converge from an unbiased uniform initial guess, and the computation time are analyzed. Some observations are noted based on the extensive implementation done in this study. Complete details of the benchmark problems and the results are included. The computer codes related to this study are made available on the internet for ready access.
Resumo:
Workstation clusters equipped with high performance interconnect having programmable network processors facilitate interesting opportunities to enhance the performance of parallel application run on them. In this paper, we propose schemes where certain application level processing in parallel database query execution is performed on the network processor. We evaluate the performance of TPC-H queries executing on a high end cluster where all tuple processing is done on the host processor, using a timed Petri net model, and find that tuple processing costs on the host processor dominate the execution time. These results are validated using a small cluster. We therefore propose 4 schemes where certain tuple processing activity is offloaded to the network processor. The first 2 schemes offload the tuple splitting activity - computation to identify the node on which to process the tuples, resulting in an execution time speedup of 1.09 relative to the base scheme, but with I/O bus becoming the bottleneck resource. In the 3rd scheme in addition to offloading tuple processing activity, the disk and network interface are combined to avoid the I/O bus bottleneck, which results in speedups up to 1.16, but with high host processor utilization. Our 4th scheme where the network processor also performs apart of join operation along with the host processor, gives a speedup of 1.47 along with balanced system resource utilizations. Further we observe that the proposed schemes perform equally well even in a scaled architecture i.e., when the number of processors is increased from 2 to 64