Harmonic Analysis of Advanced Bus-Clamping PWM Techniques

Special switching sequences can be employed in space-vector-based generation of pulsewidth-modulated (PWM) waveforms for voltage-source inverters. These sequences involve switching a phase twice, switching the second phase once, and clamping the third phase in a subcycle. Advanced bus-clamping PWM (ABCPWM) techniques have been proposed recently that employ such switching sequences. This letter studies the spectral properties of the waveforms produced by these PWM techniques. Further, analytical closed-form expressions are derived for the total rms harmonic distortion due to these techniques. It is shown that the ABCPWM techniques lead to lower distortion than conventional space vector PWM and discontinuous PWM at higher modulation indexes. The findings are validated on a 2.2-kW constant $V/f$ induction motor drive and also on a 100-kW motor drive.

Static RAM cell for ternary logic

A novel CMOS static RAM cell for ternary logic systems is described. This cell is based on the lambda diode. The operation of the cell has been simulated using the SPICE 2G program. The results of the simulation are given.

A Control Strategy for Reference Wave Adaptive Current Generation

Speed control of ac motors requires variable frequency, variable current, or variable voltage supply. Variable frequency supply can be obtained directly from a fixed frequency supply by using a frequency converter or from a dc source using inverters. In this paper a control technique for reference wave adaptive-current generation by modulating the inverter voltage is explained. Extension of this technique for three-phase induction-motor speed control is briefly explained. The oscillograms of the current waveforms obtained from the experimental setup are also shown.

System integration design in MEMS - A case study of micromachined load cell

One of the critical issues in large scale commercial exploitation of MEMS technology is its system integration. In MEMS, a system design approach requires integration of varied and disparate subsystems with one of a kind interface. The physical scales as well as the magnitude of signals of various subsystems vary widely. Known and proven integration techniques often lead to considerable loss in advantages the tiny MEMS sensors have to offer. Therefore, it becomes imperative to think of the entire system at the outset, at least in terms of the concept design. Such design entails various aspects of the system ranging from selection of material, transduction mechanism, structural configuration, interface electronics, and packaging. One way of handling this problem is the system-in-package approach that uses optimized technology for each function using the concurrent hybrid engineering approach. The main strength of this design approach is the fast time to prototype development. In the present work, we pursue this approach for a MEMS load cell to complete the process of system integration for high capacity load sensing. The system includes; a micromachined sensing gauge, interface electronics and a packaging module representing a system-in-package ready for end characterization. The various subsystems are presented in a modular stacked form using hybrid technologies. The micromachined sensing subsystem works on principles of piezo-resistive sensing and is fabricated using CMOS compatible processes. The structural configuration of the sensing layer is designed to reduce the offset, temperature drift, and residual stress effects of the piezo-resistive sensor. ANSYS simulations are carried out to study the effect of substrate coupling on sensor structure and its sensitivity. The load cell system has built-in electronics for signal conditioning, processing, and communication, taking into consideration the issues associated with resolution of minimum detectable signal. The packaged system represents a compact and low cost solution for high capacity load sensing in the category of compressive type load sensor.

Negative sequence compensation within fundamental positive sequence reference frame for a stiff micro-grid generation in a wind power system using slip ring induction machine

An isolated wind power generation scheme using slip ring induction machine (SRIM) is proposed. The proposed scheme maintains constant load voltage and frequency irrespective of the wind speed or load variation. The power circuit consists of two back-to-back connected inverters with a common dc link, where one inverter is directly connected to the rotor side of SRIM and the other inverter is connected to the stator side of the SRIM through LC filter. Developing a negative sequence compensation method to ensure that, even under the presence of unbalanced load, the generator experiences almost balanced three-phase current and most of the unbalanced current is directed through the stator side converter is the focus here. The SRIM controller varies the speed of the generator with variation in the wind speed to extract maximum power. The difference of the generated power and the load power is either stored in or extracted from a battery bank, which is interfaced to the common dc link through a multiphase bidirectional fly-back dc-dc converter. The SRIM control scheme, maximum power point extraction algorithm and the fly-back converter topology are incorporated from available literature. The proposed scheme is both simulated and experimentally verified.

RF Sputtered Er2O3 Thin Films as High-k Gate Dielectrics for Germanium MOS Devices

We report the material and electrical properties of Erbium Oxide (Er2O3) thin films grown on n-Ge (100) by RF sputtering. The properties of the films are correlated with the processing conditions. The structural characterization reveals that the films annealed at 550 degrees C, has densified as compared to the as-grown ones. Fixed oxide charges and interface charges, both of the order of 10(13)/cm(2) is observed.

Highly stable oscillator for quartz crystal thickness monitor

A highly stable oscillator used in a quartz crystal thickness monitor for monitoring the rate of evaporation and total thickness of film during thin film deposition is reported. The design aspects of the oscillator and its long term stability, which enhances the reproducibility and the performance of the thickness monitor, are discussed. The stability of the oscillator at defined conditions is tested and compared with the conventional transistorized oscillator and the IC oscillator using inverters. The oscillator is coupled to the crystal monitor and its performance is studied in an evaporation system by evaporating different materials

A Novel Bandwidth Enhancement Technique for Cascode Amplifier

In this paper, a new technique is presented to increase the bandwidth for a single stage amplifier. Usually, -3 dB bandwidth of single stage amplifier is in few MHz. High output impedance and subsequent capacitive loading decrease the bandwidth of amplifier. The presented technique uses a load which itself acts as bandwidth enhancer. This high speed amplifier is designed on 180 nm CMOS technology, operates at 2.5 V power supply. This amplifier is succeeded by an output buffer to achieve a better linearity, high output swing and required output impedance for matching.

Low power pipelined TCAM employing mismatch dependent power allocation technique

This paper presents design of a Low power 256x72 bit TCAM in 0.13um CMOS technology. In contrast to conventional Match line (ML) sensing scheme in which equal power is consumed irrespective of match or mismatch, the ML scheme employed in this design allocates less power to match decisions involving a large number of mismatched bits. Typically, the probability of mismatch is high so this scheme results in significant CAM power reduction. We propose to use this technique along with pipelining of search operation in which the MLs are broken into several segments. Since most words fail to match in first segment, the search operation for subsequent segments is discontinued, resulting in further reduction in power consumption. The above architecture provides 70% power reduction while performing search in 3ns.

Eye-view: A retinal image acquisition system

This paper presents a low cost but high resolution retinal image acquisition system of the human eye. The images acquired by a CMOS image sensor are communicated through the Universal Serial Bus (USB) interface to a personal computer for viewing and further processing. The image acquisition time was estimated to be 2.5 seconds. This system can also be used in telemedicine applications.

RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router

A polymorphic ASIC is a runtime reconfigurable hardware substrate comprising compute and communication elements. It is a ldquofuture proofrdquo custom hardware solution for multiple applications and their derivatives in a domain. Interoperability between application derivatives at runtime is achieved through hardware reconfiguration. In this paper we present the design of a single cycle Network on Chip (NoC) router that is responsible for effecting runtime reconfiguration of the hardware substrate. The router design is optimized to avoid FIFO buffers at the input port and loop back at output crossbar. It provides virtual channels to emulate a non-blocking network and supports a simple X-Y relative addressing scheme to limit the control overhead to 9 bits per packet. The 8times8 honeycomb NoC (RECONNECT) implemented in 130 nm UMC CMOS standard cell library operates at 500 MHz and has a bisection bandwidth of 28.5 GBps. The network is characterized for random, self-similar and application specific traffic patterns that model the execution of multimedia and DSP kernels with varying network loads and virtual channels. Our implementation with 4 virtual channels has an average network latency of 24 clock cycles and throughput of 62.5% of the network capacity for random traffic. For application specific traffic the latency is 6 clock cycles and throughput is 87% of the network capacity.

Three-level inverter fed open-end winding IM drive with common mode voltage elimination and reduced power device count

A three-level space phasor generation scheme with common mode elimination and with reduced power device count is proposed for an open end winding induction motor in this paper. The open end winding induction motor is fed by the three-level inverters from both sides. Each two level inverter is formed by cascading two two-level inverters. By sharing the bottom inverter for the two three-level inverters on either side, the power device count is reduced. The switching states with zero common mode voltage variation are selected for PWM switching so that there is no alternating common mode voltage in the pole voltages as well as in phase voltages. Only two isolated DC-links, with half the voltage rating of a conventional three-level neutral point clamped inverter, are needed for the proposed scheme.

Space-Vector-Based Hybrid Pulsewidth Modulation Techniques for Reduced Harmonic Distortion and Switching Loss

Novel switching sequences can be employed in spacevector-based pulsewidth modulation (PWM) of voltage source inverters. Differentswitching sequences are evaluated and compared in terms of inverter switching loss. A hybrid PWM technique named minimum switching loss PWM is proposed, which reduces the inverter switching loss compared to conventional space vector PWM (CSVPWM) and discontinuous PWM techniques at a given average switching frequency. Further, four space-vector-based hybrid PWM techniques are proposed that reduce line current distortion as well as switching loss in motor drives, compared to CSVPWM. Theoretical and experimental results are presented.

Low Power continuous time common mode sensing for common mode feedback circuits

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 mu m CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27-34% less power than previous high swing CMFB circuits.

High performance VLSI architecture design for H.264 CAVLC decoder

H.264 video standard achieves high quality video along with high data compression when compared to other existing video standards. H.264 uses context-based adaptive variable length coding (CAVLC) to code residual data in Baseline profile. In this paper we describe a novel architecture for CAVLC decoder including coeff-token decoder, level decoder total-zeros decoder and run-before decoder UMC library in 0.13 mu CMOS technology is used to synthesize the proposed design. The proposed design reduces chip area and improves critical path performance of CAVLC decoder in comparison with [1]. Macroblock level (including luma and chroma) pipeline processing for CAVLC is implemented with an average of 141 cycles (including pipeline buffering) per macroblock at 250MHz clock frequency. To compare our results with [1] clock frequency is constrained to 125MHz. The area required for the proposed architecture is 17586 gates, which is 22.1% improvement in comparison to [1]. We obtain a throughput of 1.73 * 10(6) macroblocks/second, which is 28% higher than that reported in [1]. The proposed design meets the processing requirement of 1080HD [5] video at 30frames/seconds.