Pricing a Shared Access Link for Fair and Efficient Operation with Variable User Data Rates

The literature on pricing implicitly assumes an "infinite data" model, in which sources can sustain any data rate indefinitely. We assume a more realistic "finite data" model, in which sources occasionally run out of data; this leads to variable user data rates. Further, we assume that users have contracts with the service provider, specifying the rates at which they can inject traffic into the network. Our objective is to study how prices can be set such that a single link can be shared efficiently and fairly among users in a dynamically changing scenario where a subset of users occasionally has little data to send. User preferences are modelled by concave increasing utility functions. Further, we introduce two additional elements: a convex increasing disutility function and a convex increasing multiplicative congestion-penally function. The disutility function takes the shortfall (contracted rate minus present rate) as its argument, and essentially encourages users to send traffic at their contracted rates, while the congestion-penalty function discourages heavy users from sending excess data when the link is congested. We obtain simple necessary and sufficient conditions on prices for fair and efficient link sharing; moreover, we show that a single price for all users achieves this. We illustrate the ideas using a simple experiment.

Hydrothermal synthesis of CdTe QDs: Their luminescence quenching in the presence of bio-molecules and observation of bistable memory effect in CdTe QD/PEDOT:PSS heterostructure

We report one-pot hydrothermal synthesis of nearly mono-disperse 3-mercaptopropionic acid capped water-soluble cadmium telluride (CdTe) quantum dots (QDs) using an air stable Te source. The optical and electrical characteristics were also studied here. It was shown that the hydrothermal synthesis could be tuned to synthesize nano structures of uniform size close to nanometers. The emissions of the CdTe QDs thus synthesized were in the range of 500-700 nm by varying the duration of synthesis. The full width at half maximum (FWHM) of the emission peaks is relatively narrow (40-90 nm), which indicates a nearly uniform distribution of QD size. The structural and optical properties of the QDs were characterized by transmission electron microscopy (TEM), photoluminescence (PL) and Ultraviolet-visible (UV-Vis) spectroscopy. The photoluminescence quenching of CdTe QDs in the presence of L-cysteine and DNA confirms its biocompatibility and its utility for biosensing applications. The room temperature current-voltage characteristics of QD film on ITO coated glass substrate show an electrically induced switching between states with high and low conductivities. The phenomenon is explained on the basis of charge confinement in quantum dots. (C) 2011 Elsevier B.V. All rights reserved.

High-temperature deformation processing maps for a NiTiCu shape memory alloy

The properties of widely used Ni-Ti-based shape memory alloys (SMAs) are highly sensitive to the underlying microstructure. Hence, controlling the evolution of microstructure during high-temperature deformation becomes important. In this article, the ``processing maps'' approach is utilized to identify the combination of temperature and strain rate for thermomechanical processing of a Ni(42)Ti(50)Cu(8) SMA. Uniaxial compression experiments were conducted in the temperature range of 800-1050 degrees C and at strain rate range of 10(-3) and 10(2) s(-1). Two-dimensional power dissipation efficiency and instability maps have been generated and various deformation mechanisms, which operate in different temperature and strain rate regimes, were identified with the aid of the maps and complementary microstructural analysis of the deformed specimens. Results show that the safe window for industrial processing of this alloy is in the range of 800-850 degrees C and at 0.1 s(-1), which leads to grain refinement and strain-free grains. Regions of the instability were identified, which result in strained microstructure, which in turn can affect the performance of the SMA.

Scalable processes for fabricating non-volatile memory devices using self-assembled 2D arrays of gold nanoparticles as charge storage nodes

We propose robust and scalable processes for the fabrication of floating gate devices using ordered arrays of 7 nm size gold nanoparticles as charge storage nodes. The proposed strategy can be readily adapted for fabricating next generation (sub-20 nm node) non-volatile memory devices.

Interference in Multiprocessor Systems with Localized Memory Access Probabilities

Past studies of memory interference in multiprocessor systems have generally assumed that the references of each processor are uniformly distributed among the memory modules. In this paper we develop a model with local referencing, which reflects more closely the behavior of real-life programs. This model is analyzed using Markov chain techniques and expressions are derived for the multiprocessor performance. New expressions are also obtained for the performance in the traditional uniform reference model and are compared with other expressions-available in the literature. Results of a simulation study are given to show the accuracy of the expressions for both models.

Stress Evolution With Temperature in Titanium-Rich NiTi Shape Memory Alloy Films

The effect of deposition temperature on residual stress evolution with temperature in Ti-rich NiTi films deposited on silicon substrates was studied. Ti-rich NiTi films were deposited on 3? Si (100) substrates by DC magnetron sputtering at three deposition temperatures (300, 350 and 400 degrees C) with subsequent annealing in vacuum at their respective deposition temperatures for 4 h. The initial value of residual stress was found to be the highest for the film deposited and annealed at 400 degrees C and the lowest for the film deposited and annealed at 300 degrees C. All the three films were found to be amorphous in the as-deposited and annealed conditions. The nature of the stress response with temperature on heating in the first cycle (room temperature to 450 degrees C) was similar for all three films although the spike in tensile stress, which occurs at similar to 330 degrees C, was significantly higher in the film deposited and annealed at 300 degrees C. All the films were also found to undergo partial crystallisation on heating up to 450 degrees C and this resulted in decrease in the stress values around 5560 degrees C in the cooling cycle. The stress response with temperature in the second thermal cycle (room temperature to 450 degrees C and back), which is reflective of the intrinsic film behaviour, was found to be similar in all cases and the elastic modulus determined from the stress response was also more or less identical. The three deposition temperatures were also not found to have a significant effect on the transformation characteristics of these films such as transformation start and finish temperatures, recovery stress and hysteresis.

A Long Memory Process Based Parametric Modeling and Recognition of PD Signal

We address the problem of recognition and retrieval of relatively weak industrial signal such as Partial Discharges (PD) buried in excessive noise. The major bottleneck being the recognition and suppression of stochastic pulsive interference (PI) which has similar time-frequency characteristics as PD pulse. Therefore conventional frequency based DSP techniques are not useful in retrieving PD pulses. We employ statistical signal modeling based on combination of long-memory process and probabilistic principal component analysis (PPCA). An parametric analysis of the signal is exercised for extracting the features of desired pules. We incorporate a wavelet based bootstrap method for obtaining the noise training vectors from observed data. The procedure adopted in this work is completely different from the research work reported in the literature, which is generally based on deserved signal frequency and noise frequency.

First passage distributions for long memory processes

We study the distribution of first passage time for Levy type anomalous diffusion. A fractional Fokker-Planck equation framework is introduced.For the zero drift case, using fractional calculus an explicit analytic solution for the first passage time density function in terms of Fox or H-functions is given. The asymptotic behaviour of the density function is discussed. For the nonzero drift case, we obtain an expression for the Laplace transform of the first passage time density function, from which the mean first passage time and variance are derived.

Non-linear electrical response of chalcogenide glasses: Memory state phenomena

Investigations on the switching behaviour of arsenic-tellurium glasses with Ge or Al additives, yield interesting information about the dependence of switching on network rigidity, co-ordination of the constituents, glass transition & ambient temperature and glass forming ability.

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip

Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the power and performance of the entire system. Further, the memory subsystem constitutes a major part (typically up to 70%) of the silicon area for the current day SoC. In this article, we address the on-chip memory architecture exploration for DSP processors which are organized as multiple memory banks, where banks can be single/dual ported with non-uniform bank sizes. In this paper we propose two different methods for physical memory architecture exploration and identify the strengths and applicability of these methods in a systematic way. Both methods address the memory architecture exploration for a given target application by considering the application's data access characteristics and generates a set of Pareto-optimal design points that are interesting from a power, performance and VLSI area perspective. To the best of our knowledge, this is the first comprehensive work on memory space exploration at physical memory level that integrates data layout and memory exploration to address the system objectives from both hardware design and application software development perspective. Further we propose an automatic framework that explores the design space identifying 100's of Pareto-optimal design points within a few hours of running on a standard desktop configuration.

Effect of selenium addition on the GeTe phase change memory alloys

Compositional dependent investigations of the bulk GeTe chalcogenides alloys added with different selenium concentrations are carried out by X-ray diffraction (XRD), Raman spectroscopy, X-ray photoelectron spectroscopy (XPS), electron probe micro-analyzer (EPMA) and differential scanning calorimetry (DSC). The measurements reveal that GeTe crystals are predominant in alloys up to 0.20 at.% of Se content indicating interstitial occupancy of Se in the Ge vacancies. Raman modes in the GeTe alloys changes to GeSe modes with the addition of Se. Amorphousness in the alloy increases with increase of Se and 0.50 at.% Se alloy forms a homogeneous amorphous phase with a mixture of Ge-Se and Te-Se bonds. Structural changes are explained with the help of bond theory of solids. Crystallization temperature is found to be increasing with increase of Se, which will enable the amorphous stability. For the optimum 0.50 at.% Se alloy, the melting temperature has reduced which will reduce the RESET current requirement for the phase change memory applications. (C) 2012 Elsevier B.V. All rights reserved.

Probabilistic Shared Cache Management (PriSM)

Effective sharing of the last level cache has a significant influence on the overall performance of a multicore system. We observe that existing solutions control cache occupancy at a coarser granularity, do not scale well to large core counts and in some cases lack the flexibility to support a variety of performance goals. In this paper, we propose Probabilistic Shared Cache Management (PriSM), a framework to manage the cache occupancy of different cores at cache block granularity by controlling their eviction probabilities. The proposed framework requires only simple hardware changes to implement, can scale to larger core count and is flexible enough to support a variety of performance goals. We demonstrate the flexibility of PriSM, by computing the eviction probabilities needed to achieve goals like hit-maximization, fairness and QOS. PriSM-HitMax improves performance by 18.7% over LRU and 11.8% over previously proposed schemes in a sixteen core machine. PriSM-Fairness improves fairness over existing solutions by 23.3% along with a performance improvement of 19.0%. PriSM-QOS successfully achieves the desired QOS targets.