Implementation of conditional phase-shift gate for quantum information processing by NMR, using transition-selective pulses

Experimental realization of quantum information processing in the field of nuclear magnetic resonance (NMR) has been well established. Implementation of conditional phase-shift gate has been a significant step, which has lead to realization of important algorithms such as Grover's search algorithm and quantum Fourier transform. This gate has so far been implemented in NMR by using coupling evolution method. We demonstrate here the implementation of the conditional phase-shift gate using transition selective pulses. As an application of the gate, we demonstrate Grover's search algorithm and quantum Fourier transform by simulations and experiments using transition selective pulses. (C) 2002 Elsevier Science (USA). All rights reserved.

The orientational relaxation of bipolar active regions

In the mean, bipolar active regions are oriented nearly toroidally, according to Hale's polarity law, with a latitude-dependent tilt known as Joy's Law. The tilt angles of individual active regions deviate from this mean behavior and change over time. It has been found that on average the change is toward the mean angle at a rate characteristic of 4.37 days (Howard, 1996). We show that this orientational relaxation is consistent with the standard model of flux tube emergence from a deep dynamo layer. Under this scenario Joy's law results from the Coriolis effect on the rising flux tube (D'Silva and Choudhuri, 1993), and departures from it result from turbulent buffeting of the tubes (Longcope and Fisher, 1996). We show that relaxation toward Joy's angle occurs because the turbulent perturbations relax on shorter time scales than the perturbations from the Coriolis force. The turbulent perturbations relax more rapidly because they are localized to the topmost portion of the convection zone while the Coriolis perturbations are more widely distributed. If a fully-developed active region remains connected to the strong toroidal magnetic field at the base of the convection zone, its tilt will eventually disappear, leaving it aligned perfectly toroidally. On the other hand, if the flux becomes disconnected from the toroidal field the bipole will assume a tilt indicative of the location of disconnection. We compare models which are connected and disconnected from the toroidal field. Only those disconnected at points very deep in the convection zone a-re consistent with observed time scale of orientational relaxation.

Effect of Post-Metallization Hydrogen Annealing on C-V Characteristic of Zirconia Grown Using Atomic Layer Deposition

Substantial amount of fixed charge present in most of the alternative gate dielectrics gives rise to large shifts in the flat-band voltage (VFB) and charge trapping and de-trapping causes hysterectic changes on voltage cycling. Both phenomena affect stable and reliable transistor operation. In this paper we have studied for the first time the effect of post-metallization hydrogen annealing on the C-V curve of MOS capacitors employing zirconia, one of the most promising gate dielectric. Samples were annealed in hydrogen ambient for up to 30 minutes at different temperatures ranging from room temperature to 400°C. C-V measurements were done after annealing at each temperature and the hysteresis width was calculated from the C-V curves. A minimum hysteresis width of ∼35 mV was observed on annealing the sample at 200°C confirming the excellent suitability of this dielectric

Investigation on the Potential Rise and Currents in Insulated Mast Scheme with Single Tower During Stroke Interception

The insulated mast scheme for the lightning protection system can be found in a few practical designs. Many advantages over conventional protection system are some times envisaged. However, the technical literature on the analysis of such schemes and further quantification of their protection efficacy is rather scarce. As a first step to address this problem, the present work is taken up and the potential rise at the top and ground end currents in insulating mast scheme with single tower is investigated for several tower heights and pertinent values of other parameters. The quantities that are investigated are the potential difference across the insulation and ground end currents for both tower and the ground wires. Quantifications are carried out for the relevant range of stroke current front times. The influence of number of ground wires, their earthing location and to a limited extent, the length of the insulating support have been ascertained. Some relevant discussion on insulation strength is made. These findings are quite novel and aid in quantification of the practical efficacy of the insulated mast scheme. The level of induction to the support tower and possible flashover to the same are not in favour of this scheme.

Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization

With extensive use of dynamic voltage scaling (DVS) there is increasing need for voltage scalable models. Similarly, leakage being very sensitive to temperature motivates the need for a temperature scalable model as well. We characterize standard cell libraries for statistical leakage analysis based on models for transistor stacks. Modeling stacks has the advantage of using a single model across many gates there by reducing the number of models that need to be characterized. Our experiments on 15 different gates show that we needed only 23 models to predict the leakage across 126 input vector combinations. We investigate the use of neural networks for the combined PVT model, for the stacks, which can capture the effect of inter die, intra gate variations, supply voltage(0.6-1.2 V) and temperature (0 - 100degC) on leakage. Results show that neural network based stack models can predict the PDF of leakage current across supply voltage and temperature accurately with the average error in mean being less than 2% and that in standard deviation being less than 5% across a range of voltage, temperature.

Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations

We investigate the feasibility of developing a comprehensive gate delay and slew models which incorporates output load, input edge slew, supply voltage, temperature, global process variations and local process variations all in the same model. We find that the standard polynomial models cannot handle such a large heterogeneous set of input variables. We instead use neural networks, which are well known for their ability to approximate any arbitrary continuous function. Our initial experiments with a small subset of standard cell gates of an industrial 65 nm library show promising results with error in mean less than 1%, error in standard deviation less than 3% and maximum error less than 11% as compared to SPICE for models covering 0.9- 1.1 V of supply, -40degC to 125degC of temperature, load, slew and global and local process parameters. Enhancing the conventional libraries to be voltage and temperature scalable with similar accuracy requires on an average 4x more SPICE characterization runs.

Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations

We investigate the feasibility of developing a comprehensive gate delay and slew models which incorporates output load, input edge slew, supply voltage, temperature, global process variations and local process variations all in the same model. We find that the standard polynomial models cannot handle such a large heterogeneous set of input variables. We instead use neural networks, which are well known for their ability to approximate any arbitrary continuous function. Our initial experiments with a small subset of standard cell gates of an industrial 65 nm library show promising results with error in mean less than 1%, error in standard deviation less than 3% and maximum error less than 11% as compared to SPICE for models covering 0.9- 1.1 V of supply, -40degC to 125degC of temperature, load, slew and global and local process parameters. Enhancing the conventional libraries to be voltage and temperature scalable with similar accuracy requires on an average 4x more SPICE characterization runs.

Performance Enhancement of the Tunnel Field Effect Transistor using SiGe Source

Due to extremely low off state current (IOFF) and excellent sub-threshold characteristics, the tunnel field effect transistor (TFET) has attracted a lot of attention for low standby power applications. In this work, we aim to increase the on state current (ION) of the device. A novel device architecture with a SiGe source is proposed. The proposed structure shows an order of improvement in ION compared to the conventional Si structure. A process flow adaptable to conventional CMOS technology is also addressed.

Nature of Electronic States in Atomically Thin MoS(2) Field-Effect Transistors

We present low-temperature electrical transport experiments in five field-effect transistor devices consisting of monolayer, bilayer, and trilayer MoS(2) films, mechanically exfoliated onto Si/SiO(2) substrate. Our experiments reveal that the electronic states In all films are localized well up to room temperature over the experimentally accessible range of gate voltage. This manifests in two-dimensional (2D) variable range hopping (VRH) at high temperatures, while below similar to 30 K, the conductivity displays oscillatory structures In gate voltage arising from resonant tunneling at the localized sites. From the correlation energy (T(0)) of VRH and gate voltage dependence of conductivity, we suggest that Coulomb potential from trapped charges In the substrate is the dominant source of disorder in MoS(2) field-effect devices, which leads to carrier localization, as well.