Multilevel Dodecagonal Voltage Space Vector Generation using Flying Capacitor topology for Induction motor drives

In this paper, a multilevel flying capacitor inverter topology suitable for generating multilevel dodecagonal space vectors for an induction motor drive, is proposed. Because of the dodecagonal space vectors, it has increased modulation range with the absence of all 6n +/- 1, (n=odd) harmonics in the phase voltage and currents. The topology, realized by flying capacitor three level inverters feeding an open-end winding induction motor, does not suffer the neutral point voltage imbalance issues seen in NPC inverters and the capacitors have inherent charge-balancing capability with PWM control using switching state redundancies. Furthermore, the proposed technique uses lesser number of power supplies compared to cascaded H-bridge or NPC based dodecagonal schemes and has better ride-through capability. Finally, the voltage control is obtained through a simple carrier-based space vector PWM scheme implemented on a DSP.

Effect of Temperature Cycling on Conduction Mechanisms in CdTe Thin Films

CdTe thin films of 500 thickness prepared by thermal evaporation technique were analyzed for leakage current and conduction mechanisms. Metal-insulator-metal (MIM) capacitors were fabricated using these films as a dielectric. These films have many possible applications, such as passivation for infrared diodes that operate at low temperatures (80 K). Direct-current (DC) current-voltage (I-V) and capacitance-voltage (C-V) measurements were performed on these films. Furthermore, the films were subjected to thermal cycling from 300 K to 80 K and back to 300 K. Typical minimum leakage currents near zero bias at room temperature varied between 0.9 nA and 0.1 mu A, while low-temperature leakage currents were in the range of 9.5 pA to 0.5 nA, corresponding to resistivity values on the order of 10(8) a''broken vertical bar-cm and 10(10) a''broken vertical bar-cm, respectively. Well-known conduction mechanisms from the literature were utilized for fitting of measured I-V data. Our analysis indicates that the conduction mechanism in general is Ohmic for low fields < 5 x 10(4) V cm(-1), while the conduction mechanism for fields > 6 x 10(4) V cm(-1) is modified Poole-Frenkel (MPF) and Fowler-Nordheim (FN) tunneling at room temperature. At 80 K, Schottky-type conduction dominates. A significant observation is that the film did not show any appreciable degradation in leakage current characteristics due to the thermal cycling.

Composition, structure and electrical properties of DC reactive magnetron sputtered Al2O3 thin films

Thin films of alumina (Al2O3) were deposited over Si < 1 0 0 > substrates at room temperature at an oxygen gas pressure of 0.03 Pa and sputtering power of 60 W using DC reactive magnetron sputtering. The composition of the as-deposited film was analyzed by X-ray photoelectron spectroscopy and the O/Al atomic ratio was found to be 1.72. The films were then annealed in vacuum to 350, 550 and 750 degrees C and X-ray diffraction results revealed that both as-deposited and post deposition annealed films were amorphous. The surface morphology and topography of the films was studied using scanning electron microscopy and atomic force microscopy, respectively. A progressive decrease in the root mean square (RMS) roughness of the films from 1.53 nm to 0.7 nm was observed with increase in the annealing temperature. Al-Al2O3-Al thin film capacitors were then fabricated on p-type Si < 1 0 0 > substrate to study the effect of temperature and frequency on the dielectric property of the films and the results are discussed.

In-situ impedance spectroscopy of layer-by-layer self-assembly of polyelectrolytes

In-situ impedance spectroscopy of layer-by-layer self-assembly of weak polyelectrolytes is presented. Interdigitated capacitors with active area of 1×1 mm2 and electrode spacing of 5 μm are fabricated and used for this purpose. Measurement results indicate that the impedance decreases with increase in number of polyelectrolyte layers. About 2.5% of relative change in magnitude of impedance at 104.7 KHz is seen for four bi-layers of Poly(Allylamine Hydrochloride) (PAH)/Poly(Acrylic acid) (PAA). An electrical equivalent for polyelectrolyte binding is obtained.

Variable field ion traps

This paper presents a technique to vary the electric field within a cylindrical ion trap (CIT) mass spectrometer while it is in operation. In this technique, the electrodes of the CIT are split into number of mini-electrodes and different voltages are applied to these split-electrodes to achieve the desired field. In our study we have investigated two geometries of the split-electrode CIT. In the first, we retain the flat endcap electrodes of the CIT but split the ring electrode into five mini-rings. In the second configuration, we split the ring electrode of the CIT into three mini-rings and also divide the endcaps into two mini-discs. By applying different potentials to the mini-rings and mini-discs of these geometries we have shown that the field within the trap can be optimized to desired values. In our study, two different types of fields were targeted. In the first, potentials were adjusted to obtain a linear electric field and, in the second, a controlled higher order even multipole field was obtained by adjusting the potential. We have shown that the different potentials required can be derived from a single RF generator by connecting appropriate capacitor terminations to split electrodes. The field within the trap can be modified by changing the values of the external capacitors. (C) 2013 Elsevier B.V. All rights reserved.

A Reduced Device-Count Hybrid Multilevel Inverter Topology with single DC Source and Improved Fault Tolerance

A new hybrid multilevel power converter topology is presented in this paper. The proposed power converter topology uses only one DC source and floating capacitors charged to asymmetrical voltage levels, are used for generating different voltage levels. The SVPWM based control strategy used in this converter maintains the capacitor voltages at the required levels in the entire modulation range including the over-modulation region. For the voltage levels: nine and above, the number of components required in the proposed topology is significantly lower, compared to the conventional multilevel inverter topologies. The number of capacitors required in this topology reduces drastically compared to the conventional flying capacitor topology, when the number of levels in the inverter output increases. This topology has better fault tolerance, as it is capable of operating with reduced number of levels, in the entire modulation range, in the event of any failure in the H-bridges. The transient as well as the steady state performance of the nine-level version of the proposed topology is experimentally verified in the entire modulation range including the over-modulation region.

A Seventeen-level Inverter With a Single DC-link For Motor Drives

In the present paper, a novel topology for generating a 17-level inverter using three-level flying capacitor inverter and cascaded H-bridge modules with floating capacitors. The proposed circuit is analyzed and various aspects of it are presented in the paper. This circuit is experimentally verified and the results are shown. The stability of the capacitor balancing algorithm has been verified during sudden acceleration. This circuit has many pole voltage redundancies. This circuit has an advantage of balancing all the capacitor voltages instantaneously by switching through the redundancies. Another advantage of this topology is its ability to generate all the 17 pole voltages from a single DC link which enables back to back converter operation. Also, the proposed inverter can be operated at all load power factors and modulation indices. Another advantage is, if one of the H-bridges fail, the inverter can still be operated at full load with reduced number of levels.

A Harmonic Suppression Scheme for Open-End Winding Split-Phase IM Drive Using Capacitive Filters for the Full Speed Range

Voltage source inverter (VSI)-fed six-phase induction motor (IM) drives have high 6n +/- 1, n = odd-order harmonic currents. This is because these currents, driven by the corresponding harmonic voltages in the inverter output, are limited only by the stator leakage impedance, as these harmonics are absent in the back electromotive force of the motor. To suppress the harmonic currents, either bulky inductive harmonic filters or complex pulsewidth modulation (PWM) techniques have to be used. This paper proposes a harmonic elimination scheme using switched capacitor filters for a VSI-fed split-phase IM drive. Two 3-phase inverters fed from capacitors are used on the open-end side of the motor to suppress 6n +/- 1, n = odd-order harmonics. A PWM scheme that can suppress the harmonics as well as balance the capacitor voltage is also proposed. The capacitor fed inverters are switched so that the fundamental voltage is not affected, and the fundamental power is always drawn from the main inverters. The proposed scheme is verified with a detailed experimental study. The effectiveness of the scheme is demonstrated by comparing the results with those obtained by disabling the capacitor fed inverters.

Influence of O-2 flow rate on HfO2 gate dielectrics for back-gated graphene transistors

HfO2 thin films deposited on Si substrate using electron beam evaporation, are evaluated for back-gated graphene transistors. The amount of O-2 flow rate, during vaporation is optimized for 35 nm thick HfO2 films, to achieve the best optical, chemical and electrical properties. It has been observed that with increasing oxygen flow rate, thickness of the films increased and refractive index decreased due to increase in porosity resulting from the scattering of the evaporant. The films deposited at low O-2 flow rates (1 and 3 SCCM) show better optical and compositional properties. The effects of post-deposition annealing and post-metallization annealing in forming gas ambience (FGA) on the optical and electrical properties of the films have been analyzed. The film deposited at 3 SCCM O-2 flow rate shows the best properties as measured on MOS capacitors. To evaluate the performance of device properties, back-gated bilayer graphene transistors on HfO2 films deposited at two O-2 flow rates of 3 and 20 SCCM have been fabricated and characterized. The transistor with HfO2 film deposited at 3 SCCM O-2 flow rate shows better electrical properties consistent with the observations on MOS capacitor structures. This suggests that an optimum oxygen pressure is necessary to get good quality films for high performance devices.

Nanostructured electrode materials for electrochemical energy storage and conversion

Manipulation of matter at the nanoscale is a way forward to move beyond our current choices in electrochemical energy storage and conversion technologies with promise of higher efficiency, environmental benignity, and cost-effectiveness. Electrochemical processes being basically surface phenomena, tailored multifunctional nanoarchitecturing can lead to improvements in terms of electronic and ionic conductivities, diffusion and mass transport, and electron transfer and electrocatalysis. The nanoscale is also a domain in which queer properties surface: those associated with conversion electrodes, ceramic particles enhancing the conductivity of polymer electrolytes, and transition metal oxide powders catalyzing fuel cell reactions, to cite a few. Although this review attempts to present a bird's eye view of the vast literature that has accumulated in this rather infant field, it also lists a few representative studies that establish the beneficial effects of going `nano'. Investigations on nanostructuring and use of nanoparticles and nanoarchitectures related to lithium-ion batteries (active materials and electrolytes), supercapacitors (electrical double-layer capacitors, supercapacitors based on pseudo-capacitance, and hybrid supercapacitors), and fuel cells (electrocatalysts, membranes and hydrogen storage materials) are highlighted. (C) 2012 John Wiley & Sons, Ltd.

Performance comparison for 12 V lead-carbon hybrid ultracapacitors with substrate-integrated and conventional pasted positive plates

Lead-carbon hybrid ultracapacitors comprise positive lead dioxide plates of the lead-acid battery and negative plates of carbon-based electrical double-layer capacitors (EDLCs). Accordingly, a lead-carbon hybrid ultracapacitor has the features of both the battery and that of an EDLC. In this study, the development and performance comparison between the two types of lead-carbon hybrid ultracapacitors, namely those with substrate-integrated and conventional pasted positive plates, is presented as such a study is lacking in the literature. The study suggests that the faradaic efficiencies for both types of lead-carbon hybrid ultracapacitors are comparable. However, their capacitance values as well as energy and power densities differ significantly. For substrate-integrated positive plate hybrid ultracapacitor, capacitance and energy density values are lower, but power density values are higher than pasted positive plate lead-carbon hybrid ultracapacitors due to their shorter response time. Accordingly, internal resistance values are also lower for substrate-integrated lead-carbon hybrid ultracapacitors. Both types of lead-carbon hybrid ultracapacitors exhibit good cycle life of 100,000 pulse charge-discharge cycles with only a nominal loss in their capacitance values.

A unique strategy towards high dielectric constant and low loss with multiwall carbon nanotubes anchored onto graphene oxide sheets

Multiwall carbon nanotubes (MWNTs) were anchored onto graphene oxide sheets (GOs) via diazonium and C-C coupling reactions and characterized by spectroscopic and electron microscopic techniques. The thus synthesized MWNT-GO hybrid was then melt mixed with 50/50 polyamide6-maleic anhydride-modified acrylonitrile-butadiene-styrene (PA6-mABS) blend to design materials with high dielectric constant (30) and low dielectric loss. The phase morphology was studied by SEM and it was observed that the MWNT-GO hybrid was selectively localized in the PA6 phase of the blend. The 30 scales with the concentration of MWNT-GO in the blends, which interestingly showed a very low dielectric loss (< 0.2) making them potential candidate for capacitors. In addition, the dynamic storage modulus scales with the fraction of MWNT-GO in the blends, demonstrating their reinforcing capability as well.

Seventeen-Level Inverter Formed by Cascading Flying Capacitor and Floating Capacitor H-Bridges

A multilevel inverter for generating 17 voltage levels using a three-level flying capacitor inverter and cascaded H-bridge modules with floating capacitors has been proposed. Various aspects of the proposed inverter like capacitor voltage balancing have been presented in the present paper. Experimental results are presented to study the performance of the proposed converter. The stability of the capacitor balancing algorithm has been verified both during transients and steady-state operation. All the capacitors in this circuit can be balanced instantaneously by using one of the pole voltage combinations. Another advantage of this topology is its ability to generate all the voltages from a single dc-link power supply which enables back-to-back operation of converter. Also, the proposed inverter can be operated at all load power factors and modulation indices. Additional advantage is, if one of the H-bridges fail, the inverter can still be operated at full load with reduced number of levels. This configuration has very low dv/dt and common-mode voltage variation.

Growth of TiO2 Films by RF Magnetron Sputtering for MOS Gate Dielectrics: Influence of Substrate Temperature

Titanium dioxide thin films were deposited by RF reactive magnetron sputtering technique on p-type silicon(100) substrates held at temperatures in the range 303-673 K. The influence of substrate temperature on the core level binding energies, chemical bonding configuration, crystallographic structure and dielectric properties was investigated. X-ray photoelectron spectroscopy studies and Fourier transform infrared transmittance data confirmed the formation of stoichiometric films with anatase phase at a substrate temperature of 673 K. The films formed at 303 K were nanocrystalline with amorphous matrix while those deposited at 673 K were transformed in to crystalline phase and growth of grains in pyramidal like structure as confirmed by X-ray diffraction and atomic force microscopy respectively. Metal-oxide-semiconductor capacitors were fabricated with the configuration of Al/TiO2/Si structures. The current voltage, capacitance voltage and conductance voltage characteristics were studied to understand the electrical conduction and dielectric properties of the MOS devices. The leakage current density (at gate voltage of 2 V) decreased from 2.2 x 10(-6) to 1.7 x 10(-7) A/cm(2), the interface trap density decreased from 1.2 x 10(13) to 2.1 x 10(12) cm(-2) eV(-1) and the dielectric constant increased from 14 to 36 with increase of substrate temperature from 303 to 673 K.

Active Power Decoupling with Reduced Converter Stress for Single-Phase Power Conversion and Interfacing

Single-phase DC/AC power electronic converters suffer from pulsating power at double the line frequency. The commonest practice to handle the issue is to provide a huge electrolytic capacitor for smoothening out the ripple. But, the electrolytic capacitors having short end of lifetimes limit the overall lifetime of the converter. Another way of handling the ripple power is by active power decoupling (APD) using the storage devices and a set of semiconductor switches. Here, a novel topology has been proposed implementing APD. The topology claims the benefit of 1) reduced stress on converter switches 2) using smaller capacitance value thus alleviating use of electrolytic capacitor in turn improving the lifetime of the converter. The circuit consists of a third leg, a storage capacitor and a storage inductor. The analysis and the simulation results are shown to prove the effectiveness of the topology.