A New Structure Preserving Energy Function Incorporating Transmission Line Resistances

A novel method to account for the transmission line resistances in structure preserving energy functions (SPEF) is presented in this paper. The method exploits the equivalence of a lossy network having the same conductance to susceptance ratio for all its elements to a lossless network with a new set of power injections. The system equations and the energy function are developed using centre of inertia (COI) variables and the loads are modelled as arbitrary functions of respective bus voltages. The application of SPEF to direct transient stability evaluation is presented considering a realistic power system example.

Power System Stability Enhancement by Single Network Adaptive Critic Stabilizers

This paper proposes a Single Network Adaptive Critic (SNAC) based Power System Stabilizer (PSS) for enhancing the small-signal stability of power systems over a wide range of operating conditions. SNAC uses only a single critic neural network instead of the action-critic dual network architecture of typical adaptive critic designs. SNAC eliminates the iterative training loops between the action and critic networks and greatly simplifies the training procedure. The performance of the proposed PSS has been tested on a Single Machine Infinite Bus test system for various system and loading conditions. The proposed stabilizer, which is relatively easier to synthesize, consistently outperformed stabilizers based on conventional lead-lag and linear quadratic regulator designs.

DTC Technique for Induction Machine based Integrated Starter-Generator of an Automobile

This paper mainly concentrates on the application of the direct torque control (DTC) technique for the induction machine based integrated startergenerator (ISG) for automobile applications. It also discusses in brief about the higher DC bus voltage requirements in the automobiles i.e. present 14V system vs. 42V system to meet the power requirements, modes of operation of ISG, electric machine and the drive selection for the ISG,description of DTC technique, simulation and experimental results, and implementation.

Medium access control schemes for local area networks with multiple priority function

This paper deals with the development and performance evaluation of three modified versions of a scheme proposed for medium access control in local area networks. The original scheme implements a collision-free and fair medium arbitration by using a control wire in conjunction with a data bus. The modifications suggested in this paper are intended to realize the multiple priority function in local area networks.

Direct stability evaluation of power systems with detailed generator models using structure-preserving energy functions

Energy-based direct methods for transient stability analysis are potentially useful both as offline tools for planning purposes as well as for online security assessment. In this paper, a novel structure-preserving energy function (SPEF) is developed using the philosophy of structure-preserving model for the system and detailed generator model including flux decay, transient saliency, automatic voltage regulator (AVR), exciter and damper winding. A simpler and yet general expression for the SPEF is also derived which can simplify the computation of the energy function. The system equations and the energy function are derived using the centre-of-inertia (COI) formulation and the system loads are modelled as arbitrary functions of the respective bus voltages. Application of the proposed SPEF to transient stability evaluation of power systems is illustrated with numerical examples.

Dynamic security assessment of power systems using structure-preserving energy functions

An application of direct methods to dynamic security assessment of power systems using structure-preserving energy functions (SPEF) is presented. The transient energy margin (TEM) is used as an index for checking the stability of the system as well as ranking the contigencies based on their severity. The computation of the TEM requires the evaluation of the critical energy and the energy at fault clearing. Usually this is done by simulating the faulted trajectory, which is time-consuming. In this paper, a new algorithm which eliminates the faulted trajectory estimation is presented to calculate the TEM. The system equations and the SPEF are developed using the centre-of-inertia (COI) formulation and the loads are modelled as arbitrary functions of the respective bus voltages. The critical energy is evaluated using the potential energy boundary surface (PEBS) method. The method is illustrated by considering two realistic power system examples.

Geometrically simple linear weirs using circular quadrants

A detailed theoretical analysis of flow through a quadrant plate weir is made in the light of the generalized theory of proportional weirs, using a numerical optimization procedure. It is shown that the flow through the quadrant plate weir has a linear discharge-head relationship valid for certain ranges of head. It is shown that the weir is associated with a reference plane or datum from which all heads are reckoned.Further, it is shown that the measuring range of the quadrant plate weir can be considerably enhanced by extending the tangents to the quadrants at the terminals of the quadrant plate weir. The importance of this weir (when the datum of the weir lies below its crest) as an outlet weir for grit chambers is highlighted. Experiments show excellent agreement with the theory by giving a constant average coefficient of discharge.

Estimation Of Charge Transport Parameters And Equivalent Circuit For Poly Alkyl Thiophene Field-Effect Transistors

The small signal ac response is measured across the source-drain terminals of organic field-effect transistors (OFET) under dc bias to obtain the equivalent circuit parameters of poly(2,5-bis(3-tetradecylthiophen-2-yl)thieno[3,2-b]thiophene) (PBTTT) and poly(3-hexyl thiophene) (P3HT) based devices. The numerically simulated response based on these parameters is in good agreement with the experimental data for PBTTT-FET except at low frequencies, while the P3HT-FET data show significant deviations. This indicates that the interface with the metal electrode is rather complex for the latter, involving additional circuit elements arising from contact impedance or charge injection processes. Such an investigation can help in identifying the operational bottlenecks and to improve the performance of OFETs.

Power System Stabilizers Design for Interconnected Power Systems

This paper proposes a method of designing fixed parameter decentralized power system stabilizers (PSS) for interconnected multi-machine power systems. Conventional design technique using a single machine infinite bus approximation involves the frequency response estimation called the GEP(s) between the AVR input and the resultant electrical torque. This requires the knowledge of equivalent external reactance and infinite bus voltage or their estimated values at each machine. Other design techniques using P-Vr characteristics or residues are based on complete system information. In the proposed method, information available at the high voltage bus of the step-up transformer is used to set up a modified Heffron-Phillip's model. With this model it is possible to decide the structure of the PSS compensator and tune its parameters at each machine in the multi-machine environment, using only those signals that are available at the generating station. The efficacy of the proposed design technique has been evaluated on three of the most widely used test systems. The simulation results have shown that the performance of the proposed stabilizer is comparable to that which could be obtained by conventional design but without the need for the estimation and computation of external system parameters.

V-CE Sensing for IGBT Protection in NPC Three Level Converters-Causes For Spurious Trippings and Their Elimination

Neutral point clamped (NPC), three level converters with insulated gate bipolar transistor devices are very popular in medium voltage, high power applications. DC bus short circuit protection is usually done, using the sensed voltage across collector and emitter (i.e., V-CE sensing), of all the devices in a leg. This feature is accommodated with the conventional gate drive circuits used in the two level converters. The similar gate drive circuit, when adopted for NPC three level converter protection, leads to false V-CE fault signals for inner devices of the leg. The paper explains the detailed circuit behavior and reasons, which result in the occurrence of such false V-CE fault signals. This paper also illustrates that such a phenomenon shows dependence on the power factor of the supplied three-phase load. Finally, experimental results are presented to support the analysis. It is shown that the problem can be avoided by blocking out the V-CE sense fault signals of the inner devices of the leg.

Ultracapacitor Based Ride Through System for Control Power Supplies in High Power Converters

High power converters are used in variable speed induction motor drive applications. Riding through a short term power supply glitch is becoming an important requirement in these power converters. The power converter uses a large number of control circuit boards for its operation. The control power supply need to ensure that any glitch in the grid side does not affect any of these control circuit boards. A power supply failure of these control cards results in shut down of the entire system. The paper discusses the ride through system developed to overcome voltage sags and short duration outages at the power supply terminals of the control cards in these converters. A 240VA non-isolated, bi-directional buck-boost converter has been designed to be used along with a stack of ultracapacitors to achieve the same. A micro-controller based digital control platform made use of to achieve the control objective. The design of the ultracapacitor stack and the bidirectional converter is described the performance of the experimental set-up is evaluated.

A Cache coherence protocol for MIN-based multiprocessors

In this paper we present a cache coherence protocol for multistage interconnection network (MIN)-based multiprocessors with two distinct private caches: private-blocks caches (PCache) containing blocks private to a process and shared-blocks caches (SCache) containing data accessible by all processes. The architecture is extended by a coherence control bus connecting all shared-block cache controllers. Timing problems due to variable transit delays through the MIN are dealt with by introducing Transient states in the proposed cache coherence protocol. The impact of the coherence protocol on system performance is evaluated through a performance study of three phases. Assuming homogeneity of all nodes, a single-node queuing model (phase 3) is developed to analyze system performance. This model is solved for processor and coherence bus utilizations using the mean value analysis (MVA) technique with shared-blocks steady state probabilities (phase 1) and communication delays (phase 2) as input parameters. The performance of our system is compared to that of a system with an equivalent-sized unified cache and with a multiprocessor implementing a directory-based coherence protocol. System performance measures are verified through simulation.

Evaluation and improvement of generators reactive power margins in interconnected power systems

The amount of reactive power margin available in a system determines its proximity to voltage instability under normal and emergency conditions. More the reactive power margin, better is the systems security and vice-versa. A hypothetical way of improving the reactive margin of a synchronous generator is to reduce the real power generation within its mega volt-ampere (MVA) ratings. This real power generation reduction will affect its power contract agreements entered in the electricity market. Owing to this, the benefit that the generator foregoes will have to be compensated by paying them some lost opportunity cost. The objective of this study is three fold. Firstly, the reactive power margins of the generators are evaluated. Secondly, they are improved using a reactive power optimization technique and optimally placed unified power flow controllers. Thirdly, the reactive power capacity exchanges along the tie-lines are evaluated under base case and improved conditions. A detailed analysis of all the reactive power sources and sinks scattered throughout the network is carried out in the study. Studies are carried out on a real life, three zone, 72-bus equivalent Indian southern grid considering normal and contingency conditions with base case operating point and optimised results presented.

Dynamic analysis of voltage instability in AC-DC systems

This paper presents the analysis and study of voltage collapse at any converter bus in A C-DC systems considering the dynamics of DC system. The problem of voltage instability is acute when HVDC links are connected to weak AC systems, the strength determined by short circuit ratio (SCR) at the converter bus. The converter control strategies are important in determining voltage instability. Small signal analysis is used to identify critical modes and evaluate the effect of AC system strength and control parameters. A sample two-terminal DC system is studied and the results compared with those obtained from static analysis. Also, the results obtained from small signal analysis are validated with nonlinear simulation.

Saturation throughput analysis of an input queueing ATM switch with multiclass bursty traffic

In this paper we consider an N x N non-blocking, space division ATM switch with input cell queueing. At each input, the cell arrival process comprises geometrically distributed bursts of consecutive cells for the various outputs. Motivated by the fact that some input links may be connected to metropolitan area networks, and others directly to B-ISDN terminals, we study the situation where there are two classes of inputs with different values of mean burst length. We show that when inputs contend for an output, giving priority to an input with smaller expected burst length yields a saturation throughput larger than if the reverse priority is given. Further, giving priority to less bursty traffic can give better throughput than if all the inputs were occupied by this less bursty traffic. We derive the asymptotic (as N --> infinity) saturation throughputs for each priority class.