A fractional order proportional integral controller for path following and trajectory tracking of miniature air vehicles

In this paper, a fractional order proportional-integral controller is developed for a miniature air vehicle for rectilinear path following and trajectory tracking. The controller is implemented by constructing a vector field surrounding the path to be followed, which is then used to generate course commands for the miniature air vehicle. The fractional order proportional-integral controller is simulated using the fundamentals of fractional calculus, and the results for this controller are compared with those obtained for a proportional controller and a proportional integral controller. In order to analyze the performance of the controllers, four performance metrics, namely (maximum) overshoot, control effort, settling time and integral of the timed absolute error cost, have been selected. A comparison of the nominal as well as the robust performances of these controllers indicates that the fractional order proportional-integral controller exhibits the best performance in terms of ITAE while showing comparable performances in all other aspects.

Evaluating shock absorption behavior of small-sized systems under programmable electric field

A simple ball-drop impact tester is developed for studying the dynamic response of hierarchical, complex, small-sized systems and materials. The developed algorithm and set-up have provisions for applying programmable potential difference along the height of a test specimen during an impact loading; this enables us to conduct experiments on various materials and smart structures whose mechanical behavior is sensitive to electric field. The software-hardware system allows not only acquisition of dynamic force-time data at very fast sampling rate (up to 2 x 10(6) samples/s), but also application of a pre-set potential difference (up to +/- 10 V) across a test specimen for a duration determined by feedback from the force-time data. We illustrate the functioning of the set-up by studying the effect of electric field on the energy absorption capability of carbon nanotube foams of 5 x 5 x 1.2 mm(3) size under impact conditions. (C) 2014 AIP Publishing LLC.

A controller design method for 3 phase 4 wire grid connected VSI with LCL filter

Closed loop control of a grid connected VSI requires line current control and dc bus voltage control. The closed loop system comprising PR current controller and grid connected VSI with LCL filter is a higher order system. Closed loop control gain expressions are therefore difficult to obtain directly for such systems. In this work a simplified approach has been adopted to find current and voltage controller gain expressions for a 3 phase 4 wire grid connected VSI with LCL filter. The closed loop system considered here utilises PR current controller in natural reference frame and PI controller for dc bus voltage control. Asymptotic frequency response plot and gain bandwidth requirements of the system have been used for current control and voltage controller design. A simplified lower order model, derived for closed loop current control, is used for the dc bus voltage controller design. The adopted design method has been verified through experiments by comparison of the time domain response.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have implemented a Firewall with this architecture in reconflgurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results in both speed and area improvement when it is implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields. High throughput classification invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly in terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for the worst case packet size. The Firewall rule update involves only memory re-initialization in software without any hardware change.

Programming an FPGA to Emulate the Dynamics of DC Machines

This paper presents the programming an FPGA (Field Programmable Gate Array) to emulate the dynamics of DC machines. FPGA allows high speed real time simulation with high precision. The described design includes block diagram representation of DC machine, which contain all arithmetic and logical operations. The real time simulation of the machine in FPGA is controlled by user interfaces they are Keypad interface, LCD display on-line and digital to analog converter. This approach provides emulation of electrical machine by changing the parameters. Separately Exited DC machine implemented and experimental results are presented.

Dynamic analysis and simulation of a VSC based Back-to-Back HVDC link

This paper presents the modeling and analysis of a voltage source converter (VSC) based back-to-back (BTB) HVDC link. The case study considers the response to changes in the active and reactive power and disturbance caused by single line to ground (SLG) fault. The controllers at each terminal are designed to inject a variable (magnitude and phase angle) sinusoidal, balanced set of voltages to regulate/control the active and reactive power. It is also possible to regulate the converter bus (AC) voltage by controlling the injected reactive power. The analysis is carried out using both d-q model (neglecting the harmonics in the output voltages of VSC) and three phase detailed model of VSC. While the eigenvalue analysis and controller design is based on the d-q model, the transient simulation considers both models.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have Implemented a Firewall with this architecture in reconfigurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using, our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results In both speed and area Improvement when It is Implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields.High throughput classification Invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly In terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware Implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for file worst case packet size. The Firewall rule update Involves only memory re-initialiization in software without any hardware change.

Some aspects of multilevel load-frequency control of a power system

The application of multilevel control strategies for load-frequency control of interconnected power systems is assuming importance. A large multiarea power system may be viewed as an interconnection of several lower-order subsystems, with possible change of interconnection pattern during operation. The solution of the control problem involves the design of a set of local optimal controllers for the individual areas, in a completely decentralised environment, plus a global controller to provide the corrective signal to account for interconnection effects. A global controller, based on the least-square-error principle suggested by Siljak and Sundareshan, has been applied for the LFC problem. A more recent work utilises certain possible beneficial aspects of interconnection to permit more desirable system performances. The paper reports the application of the latter strategy to LFC of a two-area power system. The power-system model studied includes the effects of excitation system and governor controls. A comparison of the two strategies is also made.

Design of a Multibus-compatible colour graphics subsystem

Colour graphics subsystems can be used in a variety of applications such as high-end business graphics, low-end scientific computations, and for realtime display of process control diagrams. The design of such a subsystem is shown. This subsystem can be added to any Multibus-compatible microcomputer system. The use of an NEC 7220 graphics display controller chip has simplified the design to a considerable extent. CGRAM (CORE graphics on Multibus), a comprehensive subset of the CORE graphics standard package, is supported on the subsystem.

Structured model-following neuro-adaptive design for attitude maneuver of rigid bodies

A new structured model-following adaptive approach is presented in this paper to achieve large attitude maneuvers of rigid bodies. First, a nominal controller is designed using the dynamic inversion philosophy. Next, a neuro- adaptive design is proposed to augment the nominal design in order to assure robust performance in the presence of parameter inaccuracies as well as unknown constant external disturbances. The structured approach proposed in this paper (where kinematic and dynamic equations are handled separately), reduces the complexity of the controller structure. From simulation studies, this adaptive controller is found to be very effective in assuring robust performance.

An adaptive power-system stabiliser which cancels the negative damping torque of a synchronous generator

The paper presents a new criterion for designing a power-system stabiliser, which is that it should cancel the negative damping torque inherent in a synchronous generator and automatic voltage regulator. The method arises from analysis based on the properties of tensor invariance, but it is easily implemented, and leads to the design of an adaptive controller. Extensive computations and simulation have been performed, and laboratory tests have been conducted on a computer-controlled micromachine system. Results are presented illustrating the effectiveness of the adaptive stabiliser.

A Novel Approach for Designing Generator Excitation controllers Using the IDA-PBC Technique

This paper presents a novel approach for designing of generator excitation controllers using Interconnection and Damping Assignment Passivity Based Control (IDA-PBC) technique for a Single Machine Infinite Bus (SMIB) system that can also be directly used in a multi-machine environment. The generator system equations are modified by referencing the rotor angle with respect to the secondary of the transformer bus instead of the infinite bus. For the modified system equations, IDA-PBC is applied to stabilize the system around an operating condition. The IDA-PBC design results in a Lyapunov function for the modified system. The new control law is practically feasible and can be applied directly to multi-machine system without referring to external system parameters. The effectiveness of the proposed controller is tested on a SMIB and a 10 generator 39 bus test system for a range of operating conditions. The Proposed excitation controller has shown good performance for both small and large disturbances when compared to the performance of a conventional static exciter with power system stabilizer.

Design of a Near Optimum Regulator for a Power Plant

For systems which can be decomposed into slow and fast subsystems, a near optimum linear state regulator consisting of two subsystem regulators can be developed. Depending upon the desired criteria, either a short term (fast controller) or a long term controller (slow controller) can be easily designed with minimum computational costs. Using this approach an example of a power system supplying a cyclic load is studied and the performance of the different controllers are compared.

Tuning of PID controllers for water networks—different approaches

Better operational control of water networks can help reduce leakage, maintain pressure, and control flow. Proportional integral derivative (PID) controllers, with proper fine-tuning, can help water utility operators achieve targets faster without creating undue transients. The authors compared three tuning methods, in different test situations, involving flow and level control to different reservoirs. Although target values were reached with all three tuning methods, the methods’ performances varied significantly. The lowest performer among the three was the method most widely used in the industry—standard tuning by the Ziegler-Nichols method. Achieving better results was offline tuning by genetic algorithms. Achieving the best control, though, was a fuzzy logic–based online tuning approach—the FZPID controller. The FZPID controller had fewer overshoots and took significantly less time to tune the gains for each problem. This new tuning approach for PID controllers can be applied to a variety of problems and can increase the performance of water networks of any size and structure

Experiences With WM: A Centralised Scheduling Approach for Performance Management of IEEE 802.11 Wireless LANs

In our earlier work ([1]) we proposed WLAN Manager (or WM) a centralised controller for QoS management of infrastructure WLANs based on the IEEE 802.11 DCF standards. The WM approach is based on queueing and scheduling packets in a device that sits between all traffic flowing between the APs and the wireline LAN, requires no changes to the AP or the STAs, and can be viewed as implementing a "Split-MAC" architecture. The objectives of WM were to manage various TCP performance related issues (such as the throughput "anomaly" when STAs associate with an AP with mixed PHY rates, and upload-download unfairness induced by finite AP buffers), and also to serve as the controller for VoIP admission control and handovers, and for other QoS management measures. In this paper we report our experiences in implementing the proposals in [1]: the insights gained, new control techniques developed, and the effectiveness of the WM approach in managing TCP performance in an infrastructure WLAN. We report results from a hybrid experiment where a physical WM manages actual TCP controlled packet flows between a server and clients, with the WLAN being simulated, and also from a small physical testbed with an actual AP.