Executing Long-running Multi-component Applications on Batch Grids

Computational grids are increasingly being used for executing large multi-component scientific applications. The most widely reported advantages of application execution on grids are the performance benefits, in terms of speeds, problem sizes or quality of solutions, due to increased number of processors. We explore the possibility of improved performance on grids without increasing the application’s processor space. For this, we consider grids with multiple batch systems. We explore the challenges involved in and the advantages of executing long-running multi-component applications on multiple batch sites with a popular multi-component climate simulation application, CCSM, as the motivation.We have performed extensive simulation studies to estimate the single and multi-site execution rates of the applications for different system characteristics.Our experiments show that in many cases, multiple batch executions can have better execution rates than a single site execution.

Register Allocation and Optimal Spill code Scheduling in Software Pipelined Loops using 0-1 Integer Linear Programming Formulation

In achieving higher instruction level parallelism, software pipelining increases the register pressure in the loop. The usefulness of the generated schedule may be restricted to cases where the register pressure is less than the available number of registers. Spill instructions need to be introduced otherwise. But scheduling these spill instructions in the compact schedule is a difficult task. Several heuristics have been proposed to schedule spill code. These heuristics may generate more spill code than necessary, and scheduling them may necessitate increasing the initiation interval. We model the problem of register allocation with spill code generation and scheduling in software pipelined loops as a 0-1 integer linear program. The formulation minimizes the increase in initiation interval (II) by optimally placing spill code and simultaneously minimizes the amount of spill code produced. To the best of our knowledge, this is the first integrated formulation for register allocation, optimal spill code generation and scheduling for software pipelined loops. The proposed formulation performs better than the existing heuristics by preventing an increase in II in 11.11% of the loops and generating 18.48% less spill code on average among the loops extracted from Perfect Club and SPEC benchmarks with a moderate increase in compilation time.

Incentive compatible mechanisms for group ticket allocation in software maintenance services

A customer reported problem (or Trouble Ticket) in software maintenance is typically solved by one or more maintenance engineers. The decision of allocating the ticket to one or more engineers is generally taken by the lead, based on customer delivery deadlines and a guided complexity assessment from each maintenance engineer. The key challenge in such a scenario is two folds, un-truthful (hiked up) elicitation of ticket complexity by each engineer to the lead and the decision of allocating the ticket to a group of engineers who will solve the ticket with in customer deadline. The decision of allocation should ensure Individual and Coalitional Rationality along with Coalitional Stability. In this paper we use game theory to examine the issue of truthful elicitation of ticket complexities by engineers for solving ticket as a group given a specific customer delivery deadline. We formulate this problem as strategic form game and propose two mechanisms, (1) Division of Labor (DOL) and (2) Extended Second Price (ESP). In the proposed mechanisms we show that truth telling by each engineer constitutes a Dominant Strategy Nash Equilibrium of the underlying game. Also we analyze the existence of Individual Rationality (IR) and Coalitional Rationality (CR) properties to motivate voluntary and group participation. We use Core, solution concept from co-operative game theory to analyze the stability of the proposed group based on the allocation and payments.

A homobimetallic complex of chromium(0) with a sigma-borane component

The synthesis, characterization, and reactivity of a chromium(0) complex bearing an amine-borane moiety (eta(6)-C(6)H(5)CH(2)NMe(2)center dot BH(3))Cr(CO)(3) (2) is reported. Photolysis of complex 2 results in the elimination of a CO ligand followed by the formation of an intramolecular sigma-borane complex (eta(1)-(eta(6)- C(6)H(5)CH(2)NMe(2)center dot BH(2)-H))Cr(CO)(2) (3). This species was characterized in solution by NMR spectroscopy. Reaction of complex 2 with photochemically generated (OC)(5)Cr(THF) affords a novel homobimetallic sigma-borane complex (OC)(3)Cr(eta(6)-C(6)H(5)CH(2)NMe(2)center dot BH(2)-H-Cr(CO)(5)) (4), wherein one of the BH moieties is bound to the chromium center in an eta(1)-fashion. The sigma-borane complex 4 was isolated in moderate to good yield (72%). The BH(3) fragment in the complexes 3 and 4 are highly dynamic involving exchange of the BH hydrogen bound to the metal with the terminal BH hydrogen atoms. The dynamics has been studied using variable-temperature NMR spectroscopy. Complexes 2 and 4 have been characterized by X-ray crystallography.

Recent Advances in Low CTE and High Density System-on-a-Package (SOP) Substrate with Thin Film Component Integration

The Packaging Research Center has been developing next generation system-on-a-package (SOP) technology with digital, RF, optical, and sensor functions integrated in a single package/module. The goal of this effort is to develop a platform substrate technology providing very high wiring density and embedded thin film passive and active components using PWB compatible materials and processes. The latest SOP baseline process test vehicle has been fabricated on novel Si-matched CTE, high modulus C-SiC composite core substrates using 10mum thick BCB dielectric films with loss tangent of 0.0008 and dielectric constant of 2.65. A semi-additive plating process has been developed for multilayer microvia build-up using BCB without the use of any vacuum deposition or polishing/CMP processes. PWB and package substrate compatible processes such as plasma surface treatment/desmear and electroless/electrolytic pulse reverse plating was used. The smallest line width and space demonstrated in this paper is 6mum with microvia diameters in the 15-30mum range. This build-up process has also been developed on medium CTE organic laminates including MCL-E-679F from Hitachi Chemical and PTFE laminates with Cu-Invar-Cu core. Embedded decoupling capacitors with capacitance density of >500nF/cm2 have been integrated into the build-up layers using sol-gel synthesized BaTiO3 thin films (200-300nm film thickness) deposited on copper foils and integrated using vacuum lamination and subtractive etch processes. Thin metal alloy resistor films have been integrated into the SOP substrate using two methods: (a) NiCrAlSi thin films (25ohms per square) deposited on copper foils (Gould Electronics) laminated on the build-up layers and two step etch process for resistor definition, and (b) electroless plated Ni-W-P thin films (70 ohms to few Kohms per square) on the BCB dielectric by plasma surface treatment and activation. The electrical design and build-up layer structure along- - with key materials and processes used in the fabrication of the SOP4 test vehicle were presented in this paper. Initial results from the high density wiring and embedded thin film components were also presented. The focus of this paper is on integration of materials, processes and structures in a single package substrate for system-on-a-package (SOP) implementation

Access Control in Communication Systems

Access control is an important component in the security of communication systems. While cryptography has rightfully been a significant component in the design of large scale communication systems, its relation to access control, especially its complementarity, has not often been brought out in full. With the wide availability of SELinux, a comprehensive model of access control has all the more become important. In many large scale systems, access control and trust management have become important components in the design. In survivable systems, models of group communication systems may have to be integrated with access control models. In this paper, we discuss the problem of integrating various formalisms often encountered in large scale communication systems, especially in connection with dynamic access control policies as well as trust management

Compiler Assisted Leakage Energy Optimization for Clustered VLIW Architectures

Miniaturization of devices and the ensuing decrease in the threshold voltage has led to a substantial increase in the leakage component of the total processor energy consumption. Relatively simpler issue logic and the presence of a large number of function units in the VLIW and the clustered VLIW architectures attribute a large fraction of this leakage energy consumption in the functional units. However, functional units are not fully utilized in the VLIW architectures because of the inherent variations in the ILP of the programs. This underutilization is even more pronounced in the context of clustered VLIW architectures because of the contentions for the limited number of slow intercluster communication channels which lead to many short idle cycles.In the past, some architectural schemes have been proposed to obtain leakage energy bene .ts by aggressively exploiting the idleness of functional units. However, presence of many short idle cycles cause frequent transitions from the active mode to the sleep mode and vice-versa and adversely a ffects the energy benefits of a purely hardware based scheme. In this paper, we propose and evaluate a compiler instruction scheduling algorithm that assist such a hardware based scheme in the context of VLIW and clustered VLIW architectures. The proposed scheme exploits the scheduling slacks of instructions to orchestrate the functional unit mapping with the objective of reducing the number of transitions in functional units thereby keeping them off for a longer duration. The proposed compiler-assisted scheme obtains a further 12% reduction of energy consumption of functional units with negligible performance degradation over a hardware-only scheme for a VLIW architecture. The benefits are 15% and 17% in the context of a 2-clustered and a 4-clustered VLIW architecture respectively. Our test bed uses the Trimaran compiler infrastructure.