Distance Relay Co-ordination Using Support Vector Machines in Power Transmission System

In this paper, a new approach to enhance the transmission system distance relay co-ordination is presented. The approach depends on the apparent impedance loci seen by the distance relay during all possible disturbances. In a distance relay, the impedance loci seen at the relay location is obtained by extensive transient stability studies. Support vector machines (SVMs), a class of patterns classifiers are used in discriminating zone settings (zone-1, zone-2 and zone-3) using the signals to be used by the relay. Studies on a sample 9-bus are presented for illustrating the proposed scheme.

Grid-connected versus stand-alone energy systems for decentralized power-A review of literature

The decentralized power is characterised by generation of power nearer to the demand centers, focusing mainly on meeting local energy needs. A decentralized power system can function either in the presence of grid, where it can feed the surplus power generated to the grid, or as an independent/stand-alone isolated system exclusively meeting the local demands of remote locations. Further, decentralized power is also classified on the basis of type of energy resources used-non-renewable and renewable. These classifications along with a plethora of technological alternatives have made the whole prioritization process of decentralized power quite complicated for decision making. There is abundant literature, which has discussed various approaches that have been used to support decision making under such complex situations. We envisage that summarizing such literature and coming out with a review paper would greatly help the policy/decision makers and researchers in arriving at effective solutions. With such a felt need 102 articles were reviewed and features of several technological alternatives available for decentralized power, the studies on modeling and analysis of economic, environmental and technological asibilities of both grid-connected (GC) and stand-alone (SA) systems as decentralized power options are presented. (C) 2009 Elsevier Ltd. All rights reserved.

Single network adaptive critic design for power system stabilisers

The recently developed single network adaptive critic (SNAC) design has been used in this study to design a power system stabiliser (PSS) for enhancing the small-signal stability of power systems over a wide range of operating conditions. PSS design is formulated as a discrete non-linear quadratic regulator problem. SNAC is then used to solve the resulting discrete-time optimal control problem. SNAC uses only a single critic neural network instead of the action-critic dual network architecture of typical adaptive critic designs. SNAC eliminates the iterative training loops between the action and critic networks and greatly simplifies the training procedure. The performance of the proposed PSS has been tested on a single machine infinite bus test system for various system and loading conditions. The proposed stabiliser, which is relatively easier to synthesise, consistently outperformed stabilisers based on conventional lead-lag and linear quadratic regulator designs.

Implementation of placement and routing algorithms for computer aided design of printed circuit boards

The Printed Circuit Board (PCB) layout design is one of the most important and time consuming phases during equipment design process in all electronic industries. This paper is concerned with the development and implementation of a computer aided PCB design package. A set of programs which operate on a description of the circuit supplied by the user in the form of a data file and subsequently design the layout of a double-sided PCB has been developed. The algorithms used for the design of the PCB optimise the board area and the length of copper tracks used for the interconnections. The output of the package is the layout drawing of the PCB, drawn on a CALCOMP hard copy plotter and a Tektronix 4012 storage graphics display terminal. The routing density (the board area required for one component) achieved by this package is typically 0.8 sq. inch per IC. The package is implemented on a DEC 1090 system in Pascal and FORTRAN and SIGN(1) graphics package is used for display generation.

A new family of low-power CT/SUP 2/L circuits

A new family of low-power logic circuits, employing a multiemitter transistor input circuit and a modified complementary p-n-p n-p-n output stage, having almost the same performance as standard TTL circuits and suitable for IC use, is reported in this correspondence.

Heat transfer to power-law fluids in thermal entrance region with viscous dissipation for constant heat flux conditions

An analytical solution of the heat transfer problem with viscous dissipation for non-Newtonian fluids with power-law model in the thermal entrance region of a circular pipe and two parallel plates under constant heat flux conditions is obtained using eigenvalue approach by suitably replacing one of the boundary conditions by total energy balance equation. Analytical expressions for the wall and the bulk temperatures and the local Nusselt number are presented. The results are in close agreement with those obtained by implicit finite-difference scheme. It is found that the role of viscous dissipation on heat transfer is completely different for heating and cooling conditions at the wall. The results for the case of cooling at the wall are of interest in the design of the oil pipe line.

On Minimization of Peak Power for Scan Circuit during Test

Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current which results into supply, voltage droop and eventually yield loss. This paper proposes an efficient methodology for test vector re-ordering to achieve minimum peak power supported by the given test vector set. The proposed methodology also minimizes average power under the minimum peak power constraint. A methodology to further reduce the peak power below the minimum supported peak power, by inclusion of minimum additional vectors is also discussed. The paper defines the lower bound on peak power for a given test set. The results on several benchmarks shows that it can reduce peak power by up to 27%.

Power Minimization for CDMA under Colored Noise

Rate-constrained power minimization (PMIN) over a code division multiple-access (CDMA) channel with correlated noise is studied. PMIN is. shown to be an instance of a separable convex optimization problem subject to linear ascending constraints. PMIN is further reduced to a dual problem of sum-rate maximization (RMAX). The results highlight the underlying unity between PMIN, RMAX, and a problem closely related to PMIN but with linear receiver constraints. Subsequently, conceptually simple sequence design algorithms are proposed to explicitly identify an assignment of sequences and powers that solve PMIN. The algorithms yield an upper bound of 2N - 1 on the number of distinct sequences where N is the processing gain. The sequences generated using the proposed algorithms are in general real-valued. If a rate-splitting and multi-dimensional CDMA approach is allowed, the upper bound reduces to N distinct sequences, in which case the sequences can form an orthogonal set and be binary +/- 1-valued.

Redefine: Runtime Reconfigurable Polymorphic ASIC

Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically interoperate between different standards and their derivatives. In order to achieve high resource utilization and low power dissipation, we propose REDEFINE, a polymorphic ASIC in which specialized hardware units are replaced with basic hardware units that can create the same functionality by runtime re-composition. It is a ``future-proof'' custom hardware solution for multiple applications and their derivatives in a domain. In this article, we describe a compiler framework and supporting hardware comprising compute, storage, and communication resources. Applications described in high-level language (e.g., C) are compiled into application substructures. For each application substructure, a set of compute elements on the hardware are interconnected during runtime to form a pattern that closely matches the communication pattern of that particular application. The advantage is that the bounded CEs are neither processor cores nor logic elements as in FPGAs. Hence, REDEFINE offers the power and performance advantage of an ASIC and the hardware reconfigurability and programmability of that of an FPGA/instruction set processor. In addition, the hardware supports custom instruction pipelining. Existing instruction-set extensible processors determine a sequence of instructions that repeatedly occur within the application to create custom instructions at design time to speed up the execution of this sequence. We extend this scheme further, where a kernel is compiled into custom instructions that bear strong producer-consumer relationship (and not limited to frequently occurring sequences of instructions). Custom instructions, realized as hardware compositions effected at runtime, allow several instances of the same to be active in parallel. A key distinguishing factor in majority of the emerging embedded applications is stream processing. To reduce the overheads of data transfer between custom instructions, direct communication paths are employed among custom instructions. In this article, we present the overview of the hardware-aware compiler framework, which determines the NoC-aware schedule of transports of the data exchanged between the custom instructions on the interconnect. The results for the FFT kernel indicate a 25% reduction in the number of loads/stores, and throughput improves by log(n) for n-point FFT when compared to sequential implementation. Overall, REDEFINE offers flexibility and a runtime reconfigurability at the expense of 1.16x in power and 8x in area when compared to an ASIC. REDEFINE implementation consumes 0.1x the power of an FPGA implementation. In addition, the configuration overhead of the FPGA implementation is 1,000x more than that of REDEFINE.

Negative sequence compensation within fundamental positive sequence reference frame for a stiff micro-grid generation in a wind power system using slip ring induction machine

An isolated wind power generation scheme using slip ring induction machine (SRIM) is proposed. The proposed scheme maintains constant load voltage and frequency irrespective of the wind speed or load variation. The power circuit consists of two back-to-back connected inverters with a common dc link, where one inverter is directly connected to the rotor side of SRIM and the other inverter is connected to the stator side of the SRIM through LC filter. Developing a negative sequence compensation method to ensure that, even under the presence of unbalanced load, the generator experiences almost balanced three-phase current and most of the unbalanced current is directed through the stator side converter is the focus here. The SRIM controller varies the speed of the generator with variation in the wind speed to extract maximum power. The difference of the generated power and the load power is either stored in or extracted from a battery bank, which is interfaced to the common dc link through a multiphase bidirectional fly-back dc-dc converter. The SRIM control scheme, maximum power point extraction algorithm and the fly-back converter topology are incorporated from available literature. The proposed scheme is both simulated and experimentally verified.

Influence of Temperature and High Electric Field on Power Consumption by Piezoelectric Actuated Integrated Structure

The influence of electric field and temperature on power consumption of piezoelectric actuated integrated structure is studied by using a single degree of freedom mass-spring-damper system model coupled with a piezoactuator. The material lead zirconate titanate, is considered as it is capable of producing relatively high strains (e.g., 3000 mu epsilon). Actuators are often subject to high electric fields to increase the induced strain produced, resulting in field dependant piezoelectric coefficient d(31), dielectric coefficient epsilon(33) and dissipation factor delta. Piezostructures are also likely to be used across a wide range of temperatures in aerospace and undersea operations. Again, the piezoelectric properties can vary with temperature. Recent experimental studies by physics researchers have looked at the effect of high electric field and temperature on piezoelectric properties. These properties are used together with an impedance based power consumption model. Results show that including the nonlinear variation of dielectric permittivity and dissipation factor with electric field is important. Temperature dependence of the dielectric constant also should be considered.

Relative electrical distance concept for evaluation of network reactive power and loss contributions in a deregulated system

With the liberalisation of electricity market it has become very important to determine the participants making use of the transmission network.Transmission line usage computation requires information of generator to load contributions and the path used by various generators to meet loads and losses. In this study relative electrical distance (RED) concept is used to compute reactive power contributions from various sources like generators, switchable volt-amperes reactive(VAR) sources and line charging susceptances that are scattered throughout the network, to meet the system demands. The transmission line charge susceptances contribution to the system reactive flows and its aid extended in reducing the reactive generation at the generator buses are discussed in this paper. Reactive power transmission cost evaluation is carried out in this study. The proposed approach is also compared with other approaches viz.,proportional sharing and modified Y-bus.Detailed case studies with base case and optimised results are carried out on a sample 8-bus system. IEEE 39-bus system and a practical 72-bus system, an equivalent of Indian Southern grid are also considered for illustration and results are discussed.

Thermoelectric power in ultrathin films, quantum wires and carbon nanotubes under classically large magnetic field: Simplified theory and relative comparison

We study the thermoelectric power under classically large magnetic field (TPM) in ultrathin films (UFs), quantum wires (QWs) of non-linear optical materials on the basis of a newly formulated electron dispersion law considering the anisotropies of the effective electron masses, the spin-orbit splitting constants and the presence of the crystal field splitting within the framework of k.p formalism. The results of quantum confined III-V compounds form the special cases of our generalized analysis. The TPM has also been studied for quantum confined II-VI, stressed materials, bismuth and carbon nanotubes (CNs) on the basis of respective dispersion relations. It is found taking quantum confined CdGeAs2, InAs, InSb, CdS, stressed n-InSb and Bi that the TPM increases with increasing film thickness and decreasing electron statistics exhibiting quantized nature for all types of quantum confinement. The TPM in CNs exhibits oscillatory dependence with increasing carrier concentration and the signature of the entirely different types of quantum systems are evident from the plots. Besides, under certain special conditions, all the results for all the materials gets simplified to the well-known expression of the TPM for non-degenerate materials having parabolic energy bands, leading to the compatibility test. (C) 2009 Elsevier B.V. All rights reserved.

Power dissipation for systems with junctions of multiple quantum wires

We study power dissipation for systems of multiple quantum wires meeting at a junction, in terms of a current splitting matrix (M) describing the junction. We present a unified framework for studying dissipation for wires with either interacting electrons (i.e., Tomonaga-Luttinger liquid wires with Fermi-liquid leads) or noninteracting electrons. We show that for a given matrix M, the eigenvalues of (MM)-M-T characterize the dissipation, and the eigenvectors identify the combinations of bias voltages which need to be applied to the different wires in order to maximize the dissipation associated with the junction. We use our analysis to propose and study some microscopic models of a dissipative junction which employ the edge states of a quantum Hall liquid. These models realize some specific forms of the M matrix whose entries depends on the tunneling amplitudes between the different edges.