Transmission electron microscopy study of domain structures in ferroelectric SrBi2Nb2O9 ceramics

A transmission electron microscopy study has been carried out on the domain structures of SrBi2Nb2O9 (SBN) ferroelectric ceramics which belong to the Aurivillius family of bismuth layered perovskite oxides. SBN is a potential candidate for Ferroelectric Random access memory (FeRAM) applications. The 90° ferroelectric domains and antiphase boundaries (APBs) were identified with dark field imaging techniques using different superlattice reflections which arise as a consequence of octahedral rotations and cationic shifts. The 90° domain walls are irregular in shape without any faceting. The antiphase boundaries are less dense compared to that of SrBi2Ta2O9(SBT). The electron microscopy observations are correlated with the polarization fatigue nature of the ceramic where the domain structures possibly play a key role in the fatigue- free behavior of the Aurivillius family of ferroelectric oxides.

Interface states of laser ablated BaTiO3 and Ba0.9Ca0.1TiO3 thin films in MFS structure determined by DLTS and C – V technique

BaTiO3 and Ba0.9Ca0.1TiO3 thin films were deposited on the p – type Si substrate by pulsed excimer laser ablation technique. The Capacitance – Voltage (C-V) measurement measured at 1 MHz exhibited a clockwise rotating hysteresis loop with a wide memory window for the Metal – Ferroelectric – Semiconductor (MFS) capacitor confirming the ferroelectric nature. The low frequency C – V measurements exhibited the response of the minority carriers in the inversion region while at 1 MHz the C – V is of a high frequency type with minimum capacitance in the inversion region. The interface states of both the MFS structures were calculated from the Castagne – Vaipaille method (High – low frequency C – V curve). Deep Level Transient Spectroscopy (DLTS) was used to analyze the interface traps and capture cross section present in the MFS capacitor. There were distinct peaks present in the DLTS spectrum and these peaks were attributed to the presence of the discrete interface states present at the semiconductor – ferroelectric interface. The distribution of calculated interface states were mapped with the silicon energy band gap for both the undoped and Ca doped BaTiO3 thin films using both the C – V and DLTS method. The interface states of the Ca doped BaTiO3 thin films were found to be higher than the pure BaTiO3 thin films.

MFIS and MFS structures using SrBi2Ta2O9 thin films for the FRAM applications

Recently there is an increasing demand and extensive research on high density memories, in particular to the ferroelectric random access memory composed of 1T/1C (1 transistor/1 capacitor) or 2T/2C. FRAM's exhibit fast random acess in read/write mode, non - volatility and low power for good performance. An integration of the ferroelectric on Si is the key importance and in this regard, there had been various models proposed like MFS, MFIS, MFMIS structure etc., Choosing the proper insulator is very essential for the better performance of the device and to exhibit excellent electrical characteristics. ZrTiO4 is a potential candidate because of its excellent thermal stability and lattice match on the Si substrate. SrBi2Ta2O9 and ZrTiO4 thin films were prepared on p - type Si substrate by pulsed excimer laser ablation technique. Optimization of both ZT and SBT thin films in MFS and MFIS structure had been done based on the annealing, oxygen partial pressures and substrate temperatures to have proper texture of the thin films. The dc leakage current, P - E hysteresis, capacitance - voltage and conductance - voltage measurement were carried out. The effect of the frequency dependence on MFIS structure was observed in the C – V curve. It displays a transition of C - V curve from high frequency to low frequency curve on subjection to varied frequencies. Density of interface states has been calculated using Terman and high - low frequency C - V curve. The effect of memory window in the C - V hysteresis were analysed in terms of film thickness and annealing temperatures. DC conduction mechanism were analysed in terms of poole - frenkel, Schottky and space charge limited conduction separately on MFS, MIS structure.

MFIS and MFS structures using SrBi2Ta2O9 thin films for the FRAM applications

Recently there is an increasing demand and extensive research on high density memories, in particular to the ferroelectric random access memory composed of 1T/1C (1 transistor/1 capacitor) or 2T/2C. FRAM's exhibit fast random acess in read/write mode, non - volatility and low power for good performance. An integration of the ferroelectric on Si is the key importance and in this regard, there had been various models proposed like MFS, MFIS, MFMIS structure etc., Choosing the proper insulator is very essential for the better performance of the device and to exhibit excellent electrical characteristics. ZrTiO4 is a potential candidate because of its excellent thermal stability and lattice match on the Si substrate. SrBi2Ta2O9 and ZrTiO4 thin films were prepared on p - type Si substrate by pulsed excimer laser ablation technique. Optimization of both ZT and SBT thin films in MFS and MFIS structure had been done based on the annealing, oxygen partial pressures and substrate temperatures to have proper texture of the thin films. The dc leakage current, P - E hysteresis, capacitance - voltage and conductance - voltage measurement were carried out. The effect of the frequency dependence on MFIS structure was observed in the C – V curve. It displays a transition of C - V curve from high frequency to low frequency curve on subjection to varied frequencies. Density of interface states has been calculated using Terman and high - low frequency C - V curve. The effect of memory window in the C - V hysteresis were analysed in terms of film thickness and annealing temperatures. DC conduction mechanism were analysed in terms of poole - frenkel, Schottky and space charge limited conduction separately on MFS, MIS structure.

Design and Implementation of a Flexible and Memory Efficient Operating System for Sensor Nodes

Sensor network nodes exhibit characteristics of both embedded systems and general-purpose systems.A sensor network operating system is a kind of embedded operating system, but unlike a typical embedded operating system, sensor network operatin g system may not be real time, and is constrained by memory and energy constraints. Most sensor network operating systems are based on event-driven approach. Event-driven approach is efficient in terms of time and space.Also this approach does not require a separate stack for each execution context. But using this model, it is difficult to implement long running tasks, like cryptographic operations. A thread based computation requires a separate stack for each execution context, and is less efficient in terms of time and space. In this paper, we propose a thread based execution model that uses only a fixed number of stacks. In this execution model, the number of stacks at each priority level are fixed. It minimizes the stack requirement for multi-threading environment and at the same time provides ease of programming. We give an implementation of this model in Contiki OS by separating thread implementation from protothread implementation completely. We have tested our OS by implementing a clock synchronization protocol using it.

Micro stepping of Shape Memory Alloy based Poly Phase motor

In literature we find broadly two types of shape memory alloy based motors namely limited rotation motor and unlimited rotation motor. The unlimited rotation type SMA based motor reported in literature uses SMA springs for actuation. An attempt has been made in this paper to develop an unlimited rotation type balanced poly phase motor based on SMA wire in series with a spring in each phase. By isolating SMA actuation and spring action we are able achieve a constant force by the SMA wire through out its range of operation. The Poly phase motor can be used in stepping mode for generating incremental motion and servo mode for generating continuous motion. A method of achieving servo motion by micro stepping is presented. Micro stepping consists of controlling single-phase temperature with a position feedback. The motor has been modeled with a new approach to the SMA wire Hysterysis model. Motor is simulated for different responses and the results are compared with the experimental data.

Java Memory Model aware Software validation

The Java Memory Model (JMM) provides a semantics of Java multithreading for any implementation platform. The JMM is defined in a declarative fashion with an allowed program execution being defined in terms of existence of "commit sequences" (roughly, the order in which actions in the execution are committed). In this work, we develop OpMM, an operational under-approximation of the JMM. The immediate motivation of this work lies in integrating a formal specification of the JMM with software model checkers. We show how our operational memory model description can be integrated into a Java Path Finder (JPF) style model checker for Java programs.

Memory Architecture Exploration Framework for Cache Based Embedded SoC

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

Shape memory alloy based motor

Design and characterization of a new shape memory alloy wire based Poly Phase Motor has been reported in this paper. The motor can be used either in stepping mode or in servo mode of operation. Each phase of the motor consists of an SMA wire with a spring in series. The principle of operation of the poly phase motor is presented. The motor resembles a stepper motor in its functioning though the actuation principles are different and hence has been characterized similar to a stepper motor. The motor can be actuated in either direction with different phase sequencing methods, which are presented in this work. The motor is modelled and simulated and the results of simulations and experiments are presented. The experimental model of the motor is of dimension 150mm square, 20mm thick and uses SMA wire of 0·4mm diameter and 125mm of length in each phase.

Bit Steering In The Minimization Of Control Memory In Microprogrammed Digital-Computers

This correspondence presents an algorithm for microprogram control memory width minimization with the bit steering technique. The necessary and sufficient conditions to detect the steerability of two mutually exclusive sets of microcommands are established. The algorithm encodes the microcommands of the sets with a bit steering common part and also extends the theory to multiple (more than two) sets of microcommands.