140 resultados para hardware deskribapen lengoaiak


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Hardware constraints, which motivate receive antenna selection, also require that various antenna elements at the receiver be sounded sequentially to obtain estimates required for selecting the `best' antenna and for coherently demodulating data thereafter. Consequently, the channel state information at different antennas is outdated by different amounts and corrupted by noise. We show that, for this reason, simply selecting the antenna with the highest estimated channel gain is not optimum. Rather, a preferable strategy is to linearly weight the channel estimates of different antennas differently, depending on the training scheme. We derive closed-form expressions for the symbol error probability (SEP) of AS for MPSK and MQAM in time-varying Rayleigh fading channels for arbitrary selection weights, and validate them with simulations. We then characterize explicitly the optimal selection weights that minimize the SEP. We also consider packet reception, in which multiple symbols of a packet are received by the same antenna. New suboptimal, but computationally efficient weighted selection schemes are proposed for reducing the packet error rate. The benefits of weighted selection are also demonstrated using a practical channel code used in third generation cellular systems. Our results show that optimal weighted selection yields a significant performance gain over conventional unweighted selection.

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The technical developments and advances that have taken place thus far are reviewed in those areas impacting future phased array active aperture radar systems. The areas covered are printed circuit antennas and antenna arrays, GaAs MMIC design and fabrication leading to affordable transmitter-receiver (T-R) modules, and novel hardware and software developments. The use of fiber-optic distribution networks to interconnect the monolithically integrated optical components with the T-R modules is discussed. Beamforming and sidelobe control techniques for active phased array systems are also examined.

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Implementation details of efficient schemes for lenient execution and concurrent execution of re-entrant routines in a data flow model have been discussed in this paper. The proposed schemes require no extra hardware support and utilise the existing hardware resources such as the Matching Unit and Memory Network Interface, effectively to achieve the above mentioned goals.

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Clustered VLIW architectures solve the scalability problem associated with flat VLIW architectures by partitioning the register file and connecting only a subset of the functional units to a register file. However, inter-cluster communication in clustered architectures leads to increased leakage in functional components and a high number of register accesses. In this paper, we propose compiler scheduling algorithms targeting two previously ignored power-hungry components in clustered VLIW architectures, viz., instruction decoder and register file. We consider a split decoder design and propose a new energy-aware instruction scheduling algorithm that provides 14.5% and 17.3% benefit in the decoder power consumption on an average over a purely hardware based scheme in the context of 2-clustered and 4-clustered VLIW machines. In the case of register files, we propose two new scheduling algorithms that exploit limited register snooping capability to reduce extra register file accesses. The proposed algorithms reduce register file power consumption on an average by 6.85% and 11.90% (10.39% and 17.78%), respectively, along with performance improvement of 4.81% and 5.34% (9.39% and 11.16%) over a traditional greedy algorithm for 2-clustered (4-clustered) VLIW machine. (C) 2010 Elsevier B.V. All rights reserved.

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It is possible to sample signals at sub-Nyquist rate and still be able to reconstruct them with reasonable accuracy provided they exhibit local Fourier sparsity. Underdetermined systems of equations, which arise out of undersampling, have been solved to yield sparse solutions using compressed sensing algorithms. In this paper, we propose a framework for real time sampling of multiple analog channels with a single A/D converter achieving higher effective sampling rate. Signal reconstruction from noisy measurements on two different synthetic signals has been presented. A scheme of implementing the algorithm in hardware has also been suggested.

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A software and a microprocessor based hardware for waveform synthesis using Walsh functions are described. The software is based on Walsh function generation using Hadamard matrices and on the truncated Walsh series expansion for the waveform to be synthesized. The hardware employs six microprocessor controlled programmable Walsh function generators (PWFGs) for generating the first six non-vanishing terms of the truncated Walsh series. Improved approximation to a given waveform may be achieved by employing additional PWFGs.

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This paper presents a fast algorithm for data exchange in a network of processors organized as a reconfigurable tree structure. For a given data exchange table, the algorithm generates a sequence of tree configurations in which the data exchanges are to be executed. A significant feature of the algorithm is that each exchange is executed in a tree configuration in which the source and destination nodes are adjacent to each other. It has been proved in a theorem that for every pair of nodes in the reconfigurable tree structure, there always exists two and only two configurations in which these two nodes are adjacent to each other. The algorithm utilizes this fact and determines the solution so as to optimize both the number of configurations required and the time to perform the data exchanges. Analysis of the algorithm shows that it has linear time complexity, and provides a large reduction in run-time as compared to a previously proposed algorithm. This is well-confirmed from the experimental results obtained by executing a large number of randomly-generated data exchange tables. Another significant feature of the algorithm is that the bit-size of the routing information code is always two bits, irrespective of the number of nodes in the tree. This not only increases the speed of the algorithm but also results in simpler hardware inside each node.

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Memory models of shared memory concurrent programs define the values a read of a shared memory location is allowed to see. Such memory models are typically weaker than the intuitive sequential consistency semantics to allow efficient execution. In this paper, we present WOMM (abbreviation for Weak Operational Memory Model) that formally unifies two sources of weak behavior in hardware memory models: reordering of instructions and weakly consistent memory. We show that a large number of optimizations are allowed by WOMM. We also show that WOMM is weaker than a number of hardware memory models. Consequently, if a program behaves correctly under WOMM, it will be correct with respect to those hardware memory models. Hence, WOMM can be used as a formally specified abstraction of the hardware memory models. Moreover; unlike most weak memory models, WOMM is described using operational semantics, making it easy to integrate into a model checker for concurrent programs. We further show that WOMM has an important property - it has sequential consistency semantics for datarace-free programs.

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A new range of programmable logic devices are revolutionizing the way complex digital hardware is designed and built all over the world. Being able to test these devices in order to validate and dynamically improve on the design is crucial. This paper describes a low-cost FPGA tester that can test SRAM based FPGAs in the laboratory.

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A new class of nets, called S-nets, is introduced for the performance analysis of scheduling algorithms used in real-time systems Deterministic timed Petri nets do not adequately model the scheduling of resources encountered in real-time systems, and need to be augmented with resource places and signal places, and a scheduler block, to facilitate the modeling of scheduling algorithms. The tokens are colored, and the transition firing rules are suitably modified. Further, the concept of transition folding is used, to get intuitively simple models of multiframe real-time systems. Two generic performance measures, called �load index� and �balance index,� which characterize the resource utilization and the uniformity of workload distribution, respectively, are defined. The utility of S-nets for evaluating heuristic-based scheduling schemes is illustrated by considering three heuristics for real-time scheduling. S-nets are useful in tuning the hardware configuration and the underlying scheduling policy, so that the system utilization is maximized, and the workload distribution among the computing resources is balanced.

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This paper presents an introduction to neurocomputers and an overview of the history of neurocomputers. Direct implementation methods of neurocomputers using techniques from microelectronics and photonics are discussed. Emulation methods using special-purpose hardware are highlighted. The role of parallel computing systems for improved performance is introduced. Some commercially available neurocomputers and performance issues of such systems are also presented.

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This paper presents the design and development of a comprehensive digital protection scheme for applications in 25 KV a.c railway traction system. The scheme provides distance protection, detection of wrong phase coupling both in the lagging and leading directions, high set instantaneous trip and PT fuse failure. Provision is also made to include fault location and disturbance recording. The digital relaying scheme has been tried on two types of hardware platforms, one with PC/AT based hardware and the other with a custom designed standalone 16-bit microcontroller based card. Compared to the existing scheme, the operating time is around one cycle and the relaying algorithm has been optimised to minimise the number of computations. The prototype has been rigorously tested in the laboratory using a specially designed PC based relay test bench and the results are highly satisfactory.

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Antenna selection (AS) provides most of the benefits of multiple-antenna systems at drastically reduced hardware costs. In receive AS, the receiver connects a dynamically selected subset of N available antennas to the L available RF chains. The "best" subset to be used for data reception is determined by means of channel estimates acquired using training sequences. Due to the nature of AS, the channel estimates at different antennas are obtained from different transmissions of the pilot sequence, and are, thus, outdated by different amounts in a time-varying channel. We show that a linear weighting of the estimates is optimum for the subset selection process, where the weights are related to the temporal correlation of the channel variations. When L is not an integer divisor of N, we highlight a new issue of "training voids", in which the last pilot transmission is not fully exploited by the receiver. We present a "void-filling" method for fully exploiting these voids, which essentially provides more accurate training for some antennas, and derive the optimal subset selection rule for any void-filling method. We also derive new closed-form equations for the performance of receive AS with optimal subset selection.

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The half-duplex constraint, which mandates that a cooperative relay cannot transmit and receive simultaneously, considerably simplifies the demands made on the hardware and signal processing capabilities of a relay. However, the very inability of a relay to transmit and receive simultaneously leads to a potential under-utilization of time and bandwidth resources available to the system. We analyze the impact of the half-duplex constraint on the throughput of a cooperative relay system that uses rateless codes to harness spatial diversity and efficiently transmit information from a source to a destination. We derive closed-form expressions for the throughput of the system, and show that as the number of relays increases, the throughput approaches that of a system that uses more sophisticated full-duplex nodes. Thus, half-duplex nodes are well suited for cooperation using rateless codes despite the simplicity of both the cooperation protocol and the relays.

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Receive antenna selection (AS) provides many benefits of multiple-antenna systems at drastically reduced hardware costs. In it, the receiver connects a dynamically selected subset of N available antennas to the L available RF chains. Due to the nature of AS, the channel estimates at different antennas, which are required to determine the best subset for data reception, are obtained from different transmissions of the pilot sequence. Consequently, they are outdated by different amounts in a time-varying channel. We show that a linear weighting of the estimates is necessary and optimum for the subset selection process, where the weights are related to the temporal correlation of the channel variations. When L is not an integer divisor of N , we highlight a new issue of ``training voids'', in which the last pilot transmission is not fully exploited by the receiver. We then present new ``void-filling'' methods that exploit these voids and greatly improve the performance of AS. The optimal subset selection rules with void-filling, in which different antennas turn out to have different numbers of estimates, are also explicitly characterized. Closed-form equations for the symbol error probability with and without void-filling are also developed.