Integrated higher-order pulse-width modulation filter-transformer structure for single-phase static compensator

A power filter is necessary to connect the output of a power converter to the grid so as to reduce the harmonic distortion introduced in the line current and voltage by the power converter. Many a times, a transformer is also present before the point of common coupling. Magnetic components often constitute a significant part of the overall weight, size and cost of the grid interface scheme. So, a compact inexpensive design is desirable. A higher-order LCL-filter and a transformer are increasingly being considered for grid interconnection of the power converter. This study proposes a design method based on a three-winding transformer, that generates an integrated structure that behaves as an LCL-filter, with both the filter inductances and the transformer that are merged into a single electromagnetic component. The parameters of the transformer are derived analytically. It is shown that along with a filter capacitor, the transformer parameters provide the filtering action of an LCL-filter. A single-phase full-bridge power converter is operated as a static compensator for performance evaluation of the integrated filter transformer. A resonant integrator-based single-phase phase locked loop and stationary frame AC current controller are employed for grid frequency synchronisation and line current control, respectively.

Optimal Forwarding in Delay-Tolerant Networks With Multiple Destinations

We study the tradeoff between delivery delay and energy consumption in a delay-tolerant network in which a message (or a file) has to be delivered to each of several destinations by epidemic relaying. In addition to the destinations, there are several other nodes in the network that can assist in relaying the message. We first assume that, at every instant, all the nodes know the number of relays carrying the message and the number of destinations that have received the message. We formulate the problem as a controlled continuous-time Markov chain and derive the optimal closed-loop control (i.e., forwarding policy). However, in practice, the intermittent connectivity in the network implies that the nodes may not have the required perfect knowledge of the system state. To address this issue, we obtain an ordinary differential equation (ODE) (i.e., a deterministic fluid) approximation for the optimally controlled Markov chain. This fluid approximation also yields an asymptotically optimal open-loop policy. Finally, we evaluate the performance of the deterministic policy over finite networks. Numerical results show that this policy performs close to the optimal closed-loop policy.

Minimum switching loss pulse width modulation for reduced power conversion loss in reactive power compensators

Advanced bus-clamping switching sequences, which employ an active vector twice in a subcycle, are used to reduce line current distortion and switching loss in a space vector modulated voltage source converter. This study evaluates minimum switching loss pulse width modulation (MSLPWM), which is a combination of such sequences, for static reactive power compensator (STATCOM) application. It is shown that MSLPWM results in a significant reduction in device loss over conventional space vector pulse width modulation. Experimental verification is presented at different power levels of up to 150 kVA.

Analytical evaluation of harmonic distortion factor corresponding to generalised advanced bus-clamping pulse width modulation

A few advanced bus-clamping pulse width modulation (ABCPWM) methods have been proposed recently for a three-phase inverter. With these methods, each phase is clamped, switched at nominal frequency, and switched at twice the nominal frequency in different regions of the fundamental cycle. This study proposes a generalised ABCPWM scheme, encompassing the few ABCPWM schemes that have been proposed and many more ABCPWM schemes that have not been reported yet. Furthermore, analytical closed-form expression is derived for the harmonic distortion factor corresponding to the generalised ABCPWM. This factor is independent of load parameters. The analytical expression derived here brings out the dependence of root-mean-square (RMS) current ripple on modulation index, and can be used to evaluate the RMS current ripple corresponding to any ABCPWM scheme. The analytical closed-form expression is validated experimentally in terms of measured weighted total harmonic distortion (THD) in line voltage (V-WTHD) and measured THD in line current (I-THD) on a 6 kW induction motor drive.

Sensing of Stimulus Artifact Suppressed Signals From Electrode Interfaces

Stimulus artifacts inhibit reliable acquisition of biological evoked potentials for several milliseconds if an electrode contact is utilized for both electrical stimulation and recording purposes. This hinders the measurement of evoked short-latency biological responses, which is otherwise elicited by stimulation in implantable prosthetic devices. We present an improved stimulus artifact suppression scheme using two electrode simultaneous stimulation and differential readout using high-gain amplifiers. Substantial reduction of artifact duration has been shown possible through the common-mode rejection property of an instrumentation amplifier for electrode interfaces. The performance of this method depends on good matching of electrode-electrolyte interface properties of the chosen electrode pair. A novel calibration algorithm has been developed that helps in artificial matching of impedance and thereby achieves the required performance in artifact suppression. Stimulus artifact duration has been reduced down to 50 mu s from the stimulation-cum-recording electrodes, which is similar to 6x improvement over the present state of the art. The system is characterized with emulated resistor-capacitor loads and a variety of in-vitro metal electrodes dipped in saline environment. The proposed method is going to be useful for closed-loop electrical stimulation and recording studies, such as bidirectional neural prosthesis of retina, cochlea, brain, and spinal cord.

Investigations on Optimal Pulse-Width Modulation to Minimize Total Harmonic Distortion in the Line Current

PWM waveforms with positive voltage transition at the positive zero crossing of the fundamental voltage (type-A) are generally considered for PWM waveform with even number of switching angles per quarter whereas, waveforms with negative voltage transition at the positive zero crossing (type-B) are considered for odd number of switching angles per quarter. Optimal PWM, for minimization of total harmonic distortion of line to line (VWTHD), is generally solved with the aforementioned criteria. This paper establishes that a combination of both types of waveforms gives better performance than any individual type in terms of minimum VWTHD for complete range of modulation index (M). Optimal PWM for minimum VWTHD is solved for PWM waveforms with pulse numbers (P) of 5 and 7. Both type-A and type-B waveforms are found to be better in different ranges of M. The theoretical findings are confirmed through simulation and experimental results on a 3.7 kW squirrel cage induction motor in an open-loop V/f drive. Further, the optimal PWM is analysed from a space vector point of view.

Experimental results on low cost microcontroller based DC drive implementation

This paper presents the experimental results for an attractive control scheme implementation using an 8 bit microcontroller. The power converter involved is a 3 phase full controlled bridge rectifier. A single quadrant DC drive has been realized and results have been presented for both open and closed loop implementations.

A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs

The charge-pump (CP) mismatch current is a dominant source of static phase error and reference spur in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect. This paper presents a charge-pump (CP) mismatch current reduction technique utilizing an adaptive body bias tuning of CP transistors and a zero CP mismatch current tracking PLL architecture for reference spur suppression. A chip prototype of the proposed circuit was implemented in 0.13 mu m CMOS technology. The frequency synthesizer consumes 8.2 mA current from a 13 V supply voltage and achieves a phase noise of -96.01 dBc/Hz @ 1 MHz offset from a 2.4 GHz RF carrier. The charge-pump measurements using the proposed calibration technique exhibited a mismatch current of less than 0.3 mu A (0.55%) over the VCO control voltage range of 0.3-1.0 V. The closed loop measurements show a minimized static phase error of within +/- 70 ps and a similar or equal to 9 dB reduction in reference spur level across the PLL output frequency range 2.4-2.5 GHz. The presented CP calibration technique compensates for the DC current mismatch and the mismatch due to channel length modulation effect and therefore improves the performance of CP-PLLs in nano-meter CMOS implementations. (C) 2015 Elsevier Ltd. All rights reserved.

Quantifying the Transmit Diversity Order of Euclidean Distance Based Antenna Selection in Spatial Modulation

In this letter, we quantify the transmit diversity order of the SM system operating in a closed-loop scenario. Specifically, the SM system relying on Euclidean distance based antenna subset selection (EDAS) is considered and the achievable diversity gain is evaluated. Furthermore, the resultant trade-off between the achievable diversity gain and switching gain is studied. Simulation results confirm our theoretical results. Specifically, at a symbol error rate of about 10(-4) the signal-to-noise ratio gain achieved by EDAS is about 7 dB in case of 16-QAM and about 5 dB in case of 64-QAM.

Active Power Decoupling with Reduced Converter Stress for Single-Phase Power Conversion and Interfacing

Single-phase DC/AC power electronic converters suffer from pulsating power at double the line frequency. The commonest practice to handle the issue is to provide a huge electrolytic capacitor for smoothening out the ripple. But, the electrolytic capacitors having short end of lifetimes limit the overall lifetime of the converter. Another way of handling the ripple power is by active power decoupling (APD) using the storage devices and a set of semiconductor switches. Here, a novel topology has been proposed implementing APD. The topology claims the benefit of 1) reduced stress on converter switches 2) using smaller capacitance value thus alleviating use of electrolytic capacitor in turn improving the lifetime of the converter. The circuit consists of a third leg, a storage capacitor and a storage inductor. The analysis and the simulation results are shown to prove the effectiveness of the topology.

Thermal test method for high power three-phase grid-connected inverters

Semiconductor device junction temperatures are maintained within datasheet specified limits to avoid failure in power converters. Burn-in tests are used to ensure this. In inverters, thermal time constants can be large and burn-in tests are required to be performed over long durations of time. At higher power levels, besides increased production cost, the testing requires sources and loads that can handle high power. In this study, a novel method to test a high power three-phase grid-connected inverter is proposed. The method eliminates the need for high power sources and loads. Only energy corresponding to the losses is consumed. The test is done by circulating rated current within the three legs of the inverter. All the phase legs being loaded, the method can be used to test the inverter in both cases of a common or independent cooling arrangement for the inverter phase legs. Further, the method can be used with different inverter configurations - three- or four-wire and for different pulse width modulation (PWM) techniques. The method has been experimentally validated on a 24 kVA inverter for a four-wire configuration that uses sine-triangle PWM and a three-wire configuration that uses conventional space vector PWM.

DESIGN OF AN EXPERIMENTAL TEST FACILITY FOR SUPERCRITICAL CO2 BRAYTON CYCLE

A supercritical CO2 test facility is currently being developed at Indian Institute of Science, Bangalore, India to analyze the performance of a closed loop Brayton cycle for concentrated solar power (CSP) generation. The loop has been designed for an external heat input of 20 kW a pressure range of 75-135 bar, flow rate of 11 kg/min, and a maximum cycle temperature of 525 degrees C. The operation of the loop and the various parametric tests planned to be performed are discussed in this paper The paper addresses various aspects of the loop design with emphasis on design of various components such as regenerator and expansion device. The regenerator design is critical due to sharp property variations in CO2 occurring during the heat exchange process between the hot and cold streams. Two types of heat exchanger configurations 1) tube-in-tube (TITHE) and 2) printed circuit heat exchanger (PCHE) are analyzed and compared. A PCHE is found to be similar to 5 times compact compared to a TITHE for identical heat transfer and pressure drops. The expansion device is being custom designed to achieve the desired pressure drop for a range of operating temperatures. It is found that capillary of 5.5 mm inner diameter and similar to 2 meter length is sufficient to achieve a pressure drop from 130 to 75 bar at a maximum cycle temperature of 525 degrees C.

A Voltage Space Vector Diagram Formed by Nineteen Concentric Dodecagons for Medium-Voltage Induction Motor Drive

In this paper, a multilevel dodecagonal voltage space vector structure with nineteen concentric dodecagons is proposed for the first time. This space vector structure is achieved by cascading two sets of asymmetric three-level inverters with isolated H-bridges on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of dc link voltages and switching states of the inverters. The proposed scheme retains all the advantages of multilevel topologies as well as the advantages of dodecagonal voltage space vector structure. In addition to that, a generic and simple method for calculation of pulsewidth modulation timings using only sampled reference values (v(alpha) and v(beta)) is proposed. This enables the scheme to be used for any closed-loop application such as vector control. In addition, a new method of switching technique is proposed, which ensures minimum switching while eliminating the fifth-and seventh-order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped wave-form for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady-state operation, transient operation, including start-up have been presented and the results of fast Fourier transform analysis is also presented for validating the proposed concept.

A low-power, low-cost soil-moisture sensor using dual-probe heat-pulse technique

This paper presents the development and testing of an integrated low-power and low-cost dual-probe heat-pulse (DPHP) soil-moisture sensor in view of the electrical power consumed and affordability in developing countries. A DPHP sensor has two probes: a heater and a temperature sensor probe spaced 3 mm apart from the heater probe. Supply voltage of 3.3V is given to the heater-coil having resistance of 33 Omega power consumption of 330 mW, which is among the lowest in this category of sensors. The heater probe is 40 mm long with 2 mm diameter and hence is stiff enough to be inserted into the soil. The parametric finite element simulation study was performed to ensure that the maximum temperature rise is between 1 degrees C and 5 degrees C for wet and dry soils, respectively. The discrepancy between the simulation and experiment is less than 3.2%. The sensor was validated with white clay and tested with red soil samples to detect volumetric water-content ranging from 0% to 30%. The sensor element is integrated with low-power electronics for amplifying the output from thermocouple sensor and TelosB mote for wireless communication. A 3.7V lithium ion battery with capacity of 1150 mAh is used to power the system. The battery is charged by a 6V and 300 mA solar cell array. Readings were taken in 30 min intervals. The life-time of DPHP sensor node is around 3.6 days. The sensor, encased in 30 mm x 20 mm x 10 mm sized box, and integrated with electronics was tested independently in two separate laboratories for validating as well as investigating the dependence of the measurement of soil-moisture on the density of the soil. The difference in the readings while repeating the experiments was found out to be less than 0.01%. Furthermore, the effect of ambient temperature on the measurement of soil-moisture is studied experimentally and computationally. (C) 2015 Elsevier B.V. All rights reserved.

Active Power Decoupling with Reduced Converter Stress for Single-Phase Power Conversion and Interfacing

Single-phase DC/AC power electronic converters suffer from pulsating power at double the line frequency. The commonest practice to handle the issue is to provide a huge electrolytic capacitor for smoothening out the ripple. But, the electrolytic capacitors having short end of lifetimes limit the overall lifetime of the converter. Another way of handling the ripple power is by active power decoupling (APD) using the storage devices and a set of semiconductor switches. Here, a novel topology has been proposed implementing APD. The topology claims the benefit of 1) reduced stress on converter switches 2) using smaller capacitance value thus alleviating use of electrolytic capacitor in turn improving the lifetime of the converter. The circuit consists of a third leg, a storage capacitor and a storage inductor. The analysis and the simulation results are shown to prove the effectiveness of the topology.