48 resultados para Parallel building blocks


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Erosion resistance of pressed soil blocks used for wall construction is discussed. The spray erosion test using a standardized shower spray is discussed. Spray erosion behaviour of pressed soil blocks made out of five different soils is presented. Results of laboratory and field tests are compared. Effect of clay content of the soil and density of the pressed soil block on erosion are discussed. Also the effect of water-proof coatings on erosion of soil blocks is presented. Erosion resistance of soil blocks stabilized with organic (jaggery syrup and starch) or inorganic binders is also discussed.

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Most studies involving cement-stabilized soil blocks (CSSB) concern material properties, such as the characteristics of erosion and strength and how the composition of the block affects these properties. Moreover, research has been conducted on the performance of various mortars, investigating their material properties and the tensile bond strength between CSSB units and mortar. In contrast, very little is currently known about CSSB masonry structural behavior. Because structural design codes of traditional masonry buildings were well developed over the past century, many of the same principles may be applicable to CSSB masonry buildings. This paper details the topic of flexural behavior of CSSB masonry walls and whether the Masonry Standards Joint Committee (MSJC) code can be applied to this material for improved safety of such buildings. DOI: 10.1061/(ASCE)MT.1943-5533.0000566. (C) 2013 American Society of Civil Engineers.

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Quantum cellular automata (QCA) is a new technology in the nanometer scale and has been considered as one of the alternative to CMOS technology. In this paper, we describe the design and layout of a serial memory and parallel memory, showing the layout of individual memory cells. Assuming that we can fabricate cells which are separated by 10nm, memory capacities of over 1.6 Gbit/cm2 can be achieved. Simulations on the proposed memories were carried out using QCADesigner, a layout and simulation tool for QCA. During the design, we have tried to reduce the number of cells as well as to reduce the area which is found to be 86.16sq mm and 0.12 nm2 area with the QCA based memory cell. We have also achieved an increase in efficiency by 40%.These circuits are the building block of nano processors and provide us to understand the nano devices of the future.