Variable Sparsity Kernel Learning

This paper(1) presents novel algorithms and applications for a particular class of mixed-norm regularization based Multiple Kernel Learning (MKL) formulations. The formulations assume that the given kernels are grouped and employ l(1) norm regularization for promoting sparsity within RKHS norms of each group and l(s), s >= 2 norm regularization for promoting non-sparse combinations across groups. Various sparsity levels in combining the kernels can be achieved by varying the grouping of kernels-hence we name the formulations as Variable Sparsity Kernel Learning (VSKL) formulations. While previous attempts have a non-convex formulation, here we present a convex formulation which admits efficient Mirror-Descent (MD) based solving techniques. The proposed MD based algorithm optimizes over product of simplices and has a computational complexity of O (m(2)n(tot) log n(max)/epsilon(2)) where m is no. training data points, n(max), n(tot) are the maximum no. kernels in any group, total no. kernels respectively and epsilon is the error in approximating the objective. A detailed proof of convergence of the algorithm is also presented. Experimental results show that the VSKL formulations are well-suited for multi-modal learning tasks like object categorization. Results also show that the MD based algorithm outperforms state-of-the-art MKL solvers in terms of computational efficiency.

Synthesis of path generating flexible-link mechanisms

Flexible-link mechanisms are those linkage mechanisms (or structures) which are capable of motion by virtue of elastic deformation of one or more;links. In such mechanisms a single flexible link; can replace several rigid links and joints resulting in fewer links, fewer pin joints, reduced overall weight and reduced mechanical error. In spite of such clear advantages, contributions toward flexible-link mechanisms remain very scarce. The area of flexible-link mechanisms offers much scope for further exploration. This paper attempts to show the potential of flexible-link mechanisms in accomplishing a kinematic task like path generation. Synthesis of a four-bar mechanism with a flexible rocker for circular and straight line path generation is carried out. Displacement analysis of the structure is carried out using finite element method (FEM) and synthesis is formulated and solved as an optimization problem. Several numerical examples are presented for illustration. Based on the results obtained with these examples, the flexible-link mechanism considered shows good promise for-path generation.

Performance analysis of a modified spatial smoothing technique for direction estimation

The statistical performance analysis of ESPRIT, root-MUSIC, minimum-norm methods for direction estimation, due to finite data perturbations, using the modified spatially smoothed covariance matrix, is developed. Expressions for the mean-squared error in the direction estimates are derived based on a common framework. Based on the analysis, the use of the modified smoothed covariance matrix improves the performance of the methods when the sources are fully correlated. Also, the performance is better even when the number of subarrays is large unlike in the case of the conventionally smoothed covariance matrix. However, the performance for uncorrelated sources deteriorates due to an artificial correlation introduced by the modified smoothing. The theoretical expressions are validated using extensive simulations. (C) 1999 Elsevier Science B.V. All rights reserved.

Accelerating multi-core simulators

Simulation is an important means of evaluating new microarchitectures. With the invention of multi-core (CMP) platforms, simulators are becoming larger and more complex. However, with the availability of CMPs with larger caches and higher operating frequency, the wall clock time required for simulating an application has become comparatively shorter. Reducing this simulation time further is a great challenge, especially in the case of multi-threaded workload due to indeterminacy introduced due to simultaneously executing various threads. In this paper, we propose a technique for speeding multi-core simulation. The model of the processor core and cache are replaced with functional models, to achieve speedup. A timed Petri net model is used to estimate the execution time of the processor and the memory access latencies are estimated using hit/miss information obtained from the functional model of the cache. This model can be used to predict performance of data parallel applications or multiprogramming workload on CMP platform with various cache hierarchies and shared bus interconnect. The error in estimation of the execution time of an application is within 6%. The speedup achieved ranges between an average of 2x--4x over the cycle accurate simulator.

Thermodynamic studies on NdFeO3(s)

The enthalpy increments and the standard molar Gibbs energy of formation of NdFeO3(s) have been measured using a hightemperature Calvet microcalorimeter and a solid oxide galvanic cell, respectively. A lambda-type transition, related to magnetic order-disorder transformation (antiferromagnetic to paramagnetic), is apparent from the heat capacity data at similar to 687 K. Enthalpy increments, except in the vicinity of transition, can be represented by a polynomial expression: {Hdegrees(m)(T)-Hdegrees(m) (298.15 K)} /J(.)mol(-1) (+/- 0.7%)=-53625.6+146.0(T/K) +1.150 X 10(-4)(T/K)(2) +3.007 x 10(6)(T/K)(-1); (298.15 less than or equal to T/K less than or equal to 1000). The heat capacity, the first differential of {Hdegrees(m)(T)-Hdegrees(m)(298.15 K)}with respect to temperature, is given by Cdegrees(pm)/J(.)K(-1.)mol(-1)=146.0+ 2.30x10(-4) (T/K) - 3.007 X 10(6)(T/K)(-2). The reversible emf's of the cell, (-) Pt/{NdFeO3(s) +Nd2O3(s)+Fe(s)}//YDT/CSZ// Fe(s)+'FeO'(s)}/Pt(+), were measured in the temperature range from 1004 to 1208 K. It can be represented within experimental error by a linear equation: E/V=(0.1418 +/- 0.0003)-(3.890 +/- 0.023) x 10(-5)(T/K). The Gibbs energy of formation of solid NdFeO, calculated by the least-squares regression analysis of the data obtained in the present study, and data for Fe0.95O and Nd2O3 from the literature, is given by Delta(f)Gdegrees(m)(NdFeO3 s)/kJ (.) mol(-1)( +/- 2.0)=1345.9+0.2542(T/K); (1000 less than or equal to T/K less than or equal to 1650). The error in Delta(f)Gdegrees(m)(NdFeO3, s, T) includes the standard deviation in emf and the uncertainty in the data taken from the literature. Values of Delta(f)Hdegrees(m)(NdFeO3, s, 298.15 K) and Sdegrees(m) (NdFeO3 s, 298.15 K) calculated by the second law method are - 1362.5 (+/-6) kJ (.) mol(-1) and 123.9 (+/-2.5) J (.) K-1 (.) mol(-1), respectively. Based on the thermodynamic information, an oxygen potential diagram for the system Nd-Fe-O was developed at 1350 K. (C) 2002 Elsevier Science (USA).

On the Magnetic Ground State of La(0.85)Sr(0.15)CoO(3) Single Crystals

We present an extensive study on magnetic and transport properties of La(0.85)Sr(0.15)CoO(3) single crystals grown by a float zone method to address the issue of phase separation versus spin-glass (SG) behavior. The dc magnetization study reveals a kink in field-cooled magnetization, and the peak in the zero-field-cooling curve shifts to lower temperature at modest dc fields, indicating the SG magnetic phase. The ac susceptibility study exhibits a considerable frequency-dependent peak shift (similar to 4 K) and a time-dependent memory effect below the freezing temperature. In addition, the characteristic time scale tau(0) estimated from the frequency-dependent ac susceptibility measurement is found to be similar to 10(-13) s, which matches well with typical values observed in canonical SG systems. The transport relaxation study evidently demonstrates the time-dependent glassy phenomena. In essence, all our experimental results corroborate the existence of SG behavior in La(0.85)Sr(0.15)CoO(3) single crystals.

Notes on approximations for turbulent flows with large temperature differences

The diffusion terms in the mean velocity and temperature equations of turbulent flow are analysed to decide when variations of fluid properties can produce appreciable errors. # A theoretical demonstration is given that in the mean-flow continuity equation for a gas the error in assuming constant density is small if the flow is turbulent, even when the temperature variations are large. # Separate discussion is given of the case of local heat sources in turbulence, as large errors can occur there.

Reactive Diffusion Between Vanadium and Silicon

Interdiffusion study is conducted in the V-Si system to determine integrated diffusion coefficients of the phases. Activation energy values are calculated from the experiments conducted at different temperatures. The average values are found to be 208, 240 and 141 kJ/mol, respectively, for the V(3)Si, V(5)Si(3) and VSi(2) phases. The low activation energy for the VSi(2) phase indicates very high concentration of defects or the significant contribution from the grain boundary diffusion. The error in calculation of diffusion parameters from a very thin phase layer in a multiphase diffusion couple is discussed. Further the data available in the literature in this system is compared and the problems in the indirect methodology followed previously to calculate the diffusion parameters are discussed.

Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization

With extensive use of dynamic voltage scaling (DVS) there is increasing need for voltage scalable models. Similarly, leakage being very sensitive to temperature motivates the need for a temperature scalable model as well. We characterize standard cell libraries for statistical leakage analysis based on models for transistor stacks. Modeling stacks has the advantage of using a single model across many gates there by reducing the number of models that need to be characterized. Our experiments on 15 different gates show that we needed only 23 models to predict the leakage across 126 input vector combinations. We investigate the use of neural networks for the combined PVT model, for the stacks, which can capture the effect of inter die, intra gate variations, supply voltage(0.6-1.2 V) and temperature (0 - 100degC) on leakage. Results show that neural network based stack models can predict the PDF of leakage current across supply voltage and temperature accurately with the average error in mean being less than 2% and that in standard deviation being less than 5% across a range of voltage, temperature.

Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations

We investigate the feasibility of developing a comprehensive gate delay and slew models which incorporates output load, input edge slew, supply voltage, temperature, global process variations and local process variations all in the same model. We find that the standard polynomial models cannot handle such a large heterogeneous set of input variables. We instead use neural networks, which are well known for their ability to approximate any arbitrary continuous function. Our initial experiments with a small subset of standard cell gates of an industrial 65 nm library show promising results with error in mean less than 1%, error in standard deviation less than 3% and maximum error less than 11% as compared to SPICE for models covering 0.9- 1.1 V of supply, -40degC to 125degC of temperature, load, slew and global and local process parameters. Enhancing the conventional libraries to be voltage and temperature scalable with similar accuracy requires on an average 4x more SPICE characterization runs.

Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations

We investigate the feasibility of developing a comprehensive gate delay and slew models which incorporates output load, input edge slew, supply voltage, temperature, global process variations and local process variations all in the same model. We find that the standard polynomial models cannot handle such a large heterogeneous set of input variables. We instead use neural networks, which are well known for their ability to approximate any arbitrary continuous function. Our initial experiments with a small subset of standard cell gates of an industrial 65 nm library show promising results with error in mean less than 1%, error in standard deviation less than 3% and maximum error less than 11% as compared to SPICE for models covering 0.9- 1.1 V of supply, -40degC to 125degC of temperature, load, slew and global and local process parameters. Enhancing the conventional libraries to be voltage and temperature scalable with similar accuracy requires on an average 4x more SPICE characterization runs.

A Predictive Perfomance Model for Superscalar Processors

Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed simulation and several constraints that a processor design must satisfy. In this paper, we propose the use of empirical non-linear modeling techniques to assist processor architects in making design decisions and resolving complex trade-offs. We propose a procedure for building accurate non-linear models that consists of the following steps: (i) selection of a small set of representative design points spread across processor design space using latin hypercube sampling, (ii) obtaining performance measures at the selected design points using detailed simulation, (iii) building non-linear models for performance using the function approximation capabilities of radial basis function networks, and (iv) validating the models using an independently and randomly generated set of design points. We evaluate our model building procedure by constructing non-linear performance models for programs from the SPEC CPU2000 benchmark suite with a microarchitectural design space that consists of 9 key parameters. Our results show that the models, built using a relatively small number of simulations, achieve high prediction accuracy (only 2.8% error in CPI estimates on average) across a large processor design space. Our models can potentially replace detailed simulation for common tasks such as the analysis of key microarchitectural trends or searches for optimal processor design points.

Voltage and Temperature-Aware SSTA Using Neural Network Delay Model

With the emergence of voltage scaling as one of the most powerful power reduction techniques, it has been important to support voltage scalable statistical static timing analysis (SSTA) in deep submicrometer process nodes. In this paper, we propose a single delay model of logic gate using neural network which comprehensively captures process, voltage, and temperature variation along with input slew and output load. The number of simulation programs with integrated circuit emphasis (SPICE) required to create this model over a large voltage and temperature range is found to be modest and 4x less than that required for a conventional table-based approach with comparable accuracy. We show how the model can be used to derive sensitivities required for linear SSTA for an arbitrary voltage and temperature. Our experimentation on ISCAS 85 benchmarks across a voltage range of 0.9-1.1V shows that the average error in mean delay is less than 1.08% and average error in standard deviation is less than 2.85%. The errors in predicting the 99% and 1% probability point are 1.31% and 1%, respectively, with respect to SPICE. The two potential applications of voltage-aware SSTA have been presented, i.e., one for improving the accuracy of timing analysis by considering instance-specific voltage drops in power grids and the other for determining optimum supply voltage for target yield for dynamic voltage scaling applications.

Optimum Load Shedding Through Programming Techniques

This paper obtains a new accurate model for sensitivity in power systems and uses it in conjunction with linear programming for the solution of load-shedding problems with a minimum loss of loads. For cases where the error in the sensitivity model increases, other linear programming and quadratic programming models have been developed, assuming currents at load buses as variables and not load powers. A weighted error criterion has been used to take priority schedule into account; it can be either a linear or a quadratic function of the errors, and depending upon the function appropriate programming techniques are to be employed.

Piecewise Linearization Technique for Compact Charge Modeling of Independent DG MOSFET

Charge linearization techniques have been used over the years in advanced compact models for bulk and double-gate MOSFETs in order to approximate the position along the channel as a quadratic function of the surface potential (or inversion charge densities) so that the terminal charges can be expressed as a compact closed-form function of source and drain end surface potentials (or inversion charge densities). In this paper, in case of the independent double-gate MOSFETs, we show that the same technique could be used to model the terminal charges quite accurately only when the 1-D Poisson solution along the channel is fully hyperbolic in nature or the effective gate voltages are same. However, for other bias conditions, it leads to significant error in terminal charge computation. We further demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel actually dictates if the conventional charge linearization technique could be applied for a particular bias condition or not. Taking into account this nonlinearity, we propose a compact charge model, which is based on a novel piecewise linearization technique and shows excellent agreement with numerical and Technology Computer-Aided Design (TCAD) simulations for all bias conditions and also preserves the source/drain symmetry which is essential for Radio Frequency (RF) circuit design. The model is implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.