Optimization of the distance between source and substrate for device-grade SnS films grown by the thermal evaporation technique

Tin monosulfide (SnS) films with varying distance between the source and substrate (DSS) were prepared by the thermal evaporation technique at a temperature of 300 degrees C to investigate the effect of the DSS on the physical properties. The physical properties of the as-deposited films are strongly influenced by the variation of DSS. The thickness, Sn to S at.% ratio, grain size, and root mean square (rms) roughness of the films decreased with the increase of DSS. The films grown at DSS = 10 and 15 cm exhibited nearly single-crystalline nature with low electrical resistivity. From Hall-effect measurements, it is observed that the films grown at DSS <= 15 cm have p-type conduction and the films grown at higher distances have n-type conduction due to the variation of the Sn/S ratio. The films grown at DSS = 15 cm showed higher optical band gap of 1.36 eV as compared with the films grown at other distances. The effect of the DSS on the physical properties of SnS films is discussed and reported.

Three-level inverter fed open-end winding IM drive with common mode voltage elimination and reduced power device count

A three-level space phasor generation scheme with common mode elimination and with reduced power device count is proposed for an open end winding induction motor in this paper. The open end winding induction motor is fed by the three-level inverters from both sides. Each two level inverter is formed by cascading two two-level inverters. By sharing the bottom inverter for the two three-level inverters on either side, the power device count is reduced. The switching states with zero common mode voltage variation are selected for PWM switching so that there is no alternating common mode voltage in the pole voltages as well as in phase voltages. Only two isolated DC-links, with half the voltage rating of a conventional three-level neutral point clamped inverter, are needed for the proposed scheme.

Splitting Algorithms for Fast Relay Selection: Generalizations, Analysis, and a Unified View

Relay selection for cooperative communications promises significant performance improvements, and is, therefore, attracting considerable attention. While several criteria have been proposed for selecting one or more relays, distributed mechanisms that perform the selection have received relatively less attention. In this paper, we develop a novel, yet simple, asymptotic analysis of a splitting-based multiple access selection algorithm to find the single best relay. The analysis leads to simpler and alternate expressions for the average number of slots required to find the best user. By introducing a new contention load' parameter, the analysis shows that the parameter settings used in the existing literature can be improved upon. New and simple bounds are also derived. Furthermore, we propose a new algorithm that addresses the general problem of selecting the best Q >= 1 relays, and analyze and optimize it. Even for a large number of relays, the scalable algorithm selects the best two relays within 4.406 slots and the best three within 6.491 slots, on average. We also propose a new and simple scheme for the practically relevant case of discrete metrics. Altogether, our results develop a unifying perspective about the general problem of distributed selection in cooperative systems and several other multi-node systems.

A unified construction of space-time codes with optimal rate-diversity tradeoff

The problem of constructing space-time (ST) block codes over a fixed, desired signal constellation is considered. In this situation, there is a tradeoff between the transmission rate as measured in constellation symbols per channel use and the transmit diversity gain achieved by the code. The transmit diversity is a measure of the rate of polynomial decay of pairwise error probability of the code with increase in the signal-to-noise ratio (SNR). In the setting of a quasi-static channel model, let n(t) denote the number of transmit antennas and T the block interval. For any n(t) <= T, a unified construction of (n(t) x T) ST codes is provided here, for a class of signal constellations that includes the familiar pulse-amplitude (PAM), quadrature-amplitude (QAM), and 2(K)-ary phase-shift-keying (PSK) modulations as special cases. The construction is optimal as measured by the rate-diversity tradeoff and can achieve any given integer point on the rate-diversity tradeoff curve. An estimate of the coding gain realized is given. Other results presented here include i) an extension of the optimal unified construction to the multiple fading block case, ii) a version of the optimal unified construction in which the underlying binary block codes are replaced by trellis codes, iii) the providing of a linear dispersion form for the underlying binary block codes, iv) a Gray-mapped version of the unified construction, and v) a generalization of construction of the S-ary case corresponding to constellations of size S-K. Items ii) and iii) are aimed at simplifying the decoding of this class of ST codes.

A unified approach to bubble and drop formation

An approach, starting with the bubble formation model of Khurana and Khumar, has been presented, which is found to be reasonably applicable to the formation of both bubbles and drops from single submerged nozzles. The model treats both the phenomena jointly as the formation of a dispersed phase entity resulting from injection, whose size depends upon operating parameters and physical properties.

A Device to Crystallize Organic Solids: Structure of Ciprofloxacin, Midazolam, and Ofloxacin as Targets

The crystal structure determination of the anhydrous form of any organic compound has been a challenge because of solvent incorporation during crystallization. A device to grow anhydrous forms of low melting organic solids based on vaporization and condensation by a gradient cooling technique has been designed. Its utility has been evaluated by growing anhydrous forms of ciprofloxacin, midazolam, and ofloxacin. Ciprofloxacin crystallizes in triclinic P (1) over bar, midazolam in monoclinic P2(1)/n, and ofloxacin in the C2/c space group. Comparative studies on the conformational features with solvated structure show no significant variation in the aromatic moieties.

High performance VLSI architecture design for H.264 CAVLC decoder

H.264 video standard achieves high quality video along with high data compression when compared to other existing video standards. H.264 uses context-based adaptive variable length coding (CAVLC) to code residual data in Baseline profile. In this paper we describe a novel architecture for CAVLC decoder including coeff-token decoder, level decoder total-zeros decoder and run-before decoder UMC library in 0.13 mu CMOS technology is used to synthesize the proposed design. The proposed design reduces chip area and improves critical path performance of CAVLC decoder in comparison with [1]. Macroblock level (including luma and chroma) pipeline processing for CAVLC is implemented with an average of 141 cycles (including pipeline buffering) per macroblock at 250MHz clock frequency. To compare our results with [1] clock frequency is constrained to 125MHz. The area required for the proposed architecture is 17586 gates, which is 22.1% improvement in comparison to [1]. We obtain a throughput of 1.73 * 10(6) macroblocks/second, which is 28% higher than that reported in [1]. The proposed design meets the processing requirement of 1080HD [5] video at 30frames/seconds.

A unified model for auxiliary switch commutated DC-DC converters

A novel ZVS auxiliary switch commutated variation for all DGDC converter topologies has been proposed in 2006. With proper designation of the circuit variables (throw current I and the pole voltage V), all these converters are seen to be governed by an identical set of equations. With idealized switches, the steady-state performance is obtainable in an analytical form. The conversion ratio of the converter topologies is obtained. A generalized equivalent circuit emerges for all these converters from the steady-state conversion ratio. It also provides a dynamic model as well. With these generalized steady-state equivalent circuits, small signal analysis of these converters may be carried out readily. It enables one to use the familiar state space averaged results of the standard PWM DGDC converters for the resonant counterparts. Th dc and ac models reveals that dc and low frequency behaviour of the proposed family of converters is similiar to that of its PWM parent

Parallel circuit partitioning on a reduced array architecture

The physical design of a VLSI circuit involves circuit partitioning as a subtask. Typically, it is necessary to partition a large electrical circuit into several smaller circuits such that the total cross-wiring is minimized. This problem is a variant of the more general graph partitioning problem, and it is known that there does not exist a polynomial time algorithm to obtain an optimal partition. The heuristic procedure proposed by Kernighan and Lin1,2 requires O(n2 log2n) time to obtain a near-optimal two-way partition of a circuit with n modules. In the VLSI context, due to the large problem size involved, this computational requirement is unacceptably high. This paper is concerned with the hardware acceleration of the Kernighan-Lin procedure on an SIMD architecture. The proposed parallel partitioning algorithm requires O(n) processors, and has a time complexity of O(n log2n). In the proposed scheme, the reduced array architecture is employed with due considerations towards cost effectiveness and VLSI realizability of the architecture.The authors are not aware of any earlier attempts to parallelize a circuit partitioning algorithm in general or the Kernighan-Lin algorithm in particular. The use of the reduced array architecture is novel and opens up the possibilities of using this computing structure for several other applications in electronic design automation.

Design and performance evaluation of a systolic architecture for hidden-surface removal

In this paper, we propose a systolic architecture for hidden-surface removal. Systolic architecture is a kind of parallel architecture best known for its easy VLSI implementability. After discussing the design details of the architecture, we present the results of the simulation experiments conducted in order to evaluate the performance of the architecture.

Fabrication of device quality films of high loaded PPy/MWCNT nanocomposites using pulsed laser deposition

Polypyrrole (PPy) - multiwalled carbonnanotubes (MWCNT) nanocomposites with various MWCNT loading were prepared by in situ inversion emulsion polymerization technique. High loading of the nano filler were evaluated because of available inherent high interface area for charge separation in the nanocomposites. Solution processing of these conducting polymer nanocomposites is difficult because, most of them are insoluble in organic solvents. Device quality films of these composites were prepared by using pulsed laser deposition techniques (PLD). Comparative study of X-ray photoelectron spectroscopy (XPS) of bulk and film show that there is no chemical modification of polymer on ablation with laser. TEM images indicate PPy layer on MWCNT surface. SEM micrographs indicate that the MWCNT's are distributed throughout the film. It was observed that MWCNT in the composite held together by polymer matrix. Further more MWCNT diameter does not change from bulk to film indicating that the polymer layer remains intact during ablation. Even for very high loadings (80 wt.% of MWCNT's) of nanocomposites device quality films were fabricated, indicating laser ablation is a suitable technique for fabrication of device quality films. Conductivity of both bulk and films were measured using collinear four point probe setup. It was found that overall conductivity increases with increase in MWCNT loading. Comparative study of thickness with conductivity indicates that maximum conductivity was observed around 0.2 mu m. (C) 2010 Elsevier B.V. All rights reserved.

An integer arithmetic method to compute generalized matrix inverse and solve linear equations exactly

An algorithm that uses integer arithmetic is suggested. It transforms anm ×n matrix to a diagonal form (of the structure of Smith Normal Form). Then it computes a reflexive generalized inverse of the matrix exactly and hence solves a system of linear equations error-free.

Parallel min-cut placement on reduced hardware SIMD architecture.

Massively parallel SIMD computing is applied to obtain an order of magnitude improvement in the executional speed of an important algorithm in VLSI design automation. The physical design of a VLSI circuit involves logic module placement as a subtask. The paper is concerned with accelerating the well known Min-cut placement technique for logic cell placement. The inherent parallelism of the Min-cut algorithm is identified, and it is shown that a parallel machine based on the efficient execution of the placement procedure.