Pt-Au/C cathode with enhanced oxygen-reduction activity in PEFCs

Carbon-supported Pt-Au (Pt-Au/C) catalyst is prepared separately by impregnation, colloidal and micro-emulsion methods, and characterized by physical and electrochemical methods. Highest catalytic activity towards oxygen-reduction reaction (ORR) is exhibited by Pt-Au/C catalyst prepared by colloidal method. The optimum atomic ratio of Pt to Au in Pt-Au/C catalyst prepared by colloidal method is determined using linear-sweep and cyclic voltammetry in conjunction with cell-polarization studies. Among 3:1, 2:1 and 1:1 Pt-Au/C catalysts, (3:1) Pt-Au/C exhibits maximum electrochemical activity towards ORR. Powder X-ray diffraction pattern and transmission electron micrograph suggest Pt-Au alloy nanoparticles to be well dispersed onto the carbon-support. Energy dispersive X-ray analysis and inductively coupled plasma-optical emission spectroscopy data suggest that the atomic ratios of the alloying elements match well with the expected values. A polymer electrolyte fuel cell (PEFC) operating at 0 center dot 6 V with (3:1) Pt-Au/C cathode delivers a maximum power-density of 0 center dot 65 W/cm (2) in relation to 0 center dot 53 W/cm (2) delivered by the PEFC with pristine carbon-supported Pt cathode.

Electrical resistivity studies of benzidine-TCNQ and its inclusion compound under high pressure

Electrical resistivity studies of the charge transfer complex benzidine—TCNQ and its inclusion compound, have been carried out up to pressures 8 GPa. Two types of behaviour were observed in these complexes under high pressure and this difference is interpreted and discussed.

An optimal transform Architecture for H.264/AVC

This paper presents the design of the area optimized integer two dimensional discrete cosine transform (2-D DCT) used in H.264/AVC codecs. The 2-D DCT calculation is performed by utilizing the separability property, in such a way that 2-D DCT is divided into two 1-D DCT calculation that are joined through a common memory. Due to its area optimized approach, the design will find application in mobile devices. Verilog hardware description language (HDL) in cadence environment has been used for design, compilation, simulation and synthesis of transform block in 0.18 mu TSMC technology.