73 resultados para embedded librarian
Resumo:
Nanoembedded lead-tin alloys in aluminum matrix were synthesized by rapid solidification processing. These melt-spun aluminum alloys were then investigated using XRD, EDX and TEM. The XRD study reveals that the melt-spun samples contain elemental aluminum, lead and tin. The TEM analysis shows that embedded particles in aluminium matrix have a distinct two-phase contrast of lead and tin. The lead and tin in these nanoalloys exhibit an orientation relationship with the matrix aluminum and with each other. DSC studies were conducted to reveal the melting and solidification characteristics of these embedded nanoalloys. DSC thermograms exhibit features of multiple solidification exotherms on thermal cycling, which can be attributed to sequential melting and solidification of lead and tin in the respective alloys.
Resumo:
Nanodispersed lead in metallic and amorphous matrices was synthesized by rapid solidification processing. The optimum microstructure was tailored to avoid percolation of the particles. With these embedded particles it is possible to study quantitatively the effect of size on the superconducting transition temperature by carrying out quantitative microstructural characterization and magnetic measurements. Our results suggest the role of the matrices in enhancement or depression of superconducting transition temperature of lead. The origin of this difference in behavior with respect to different matrices and sizes is discussed.
Resumo:
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.
Resumo:
Background: Temporal analysis of gene expression data has been limited to identifying genes whose expression varies with time and/or correlation between genes that have similar temporal profiles. Often, the methods do not consider the underlying network constraints that connect the genes. It is becoming increasingly evident that interactions change substantially with time. Thus far, there is no systematic method to relate the temporal changes in gene expression to the dynamics of interactions between them. Information on interaction dynamics would open up possibilities for discovering new mechanisms of regulation by providing valuable insight into identifying time-sensitive interactions as well as permit studies on the effect of a genetic perturbation. Results: We present NETGEM, a tractable model rooted in Markov dynamics, for analyzing the dynamics of the interactions between proteins based on the dynamics of the expression changes of the genes that encode them. The model treats the interaction strengths as random variables which are modulated by suitable priors. This approach is necessitated by the extremely small sample size of the datasets, relative to the number of interactions. The model is amenable to a linear time algorithm for efficient inference. Using temporal gene expression data, NETGEM was successful in identifying (i) temporal interactions and determining their strength, (ii) functional categories of the actively interacting partners and (iii) dynamics of interactions in perturbed networks. Conclusions: NETGEM represents an optimal trade-off between model complexity and data requirement. It was able to deduce actively interacting genes and functional categories from temporal gene expression data. It permits inference by incorporating the information available in perturbed networks. Given that the inputs to NETGEM are only the network and the temporal variation of the nodes, this algorithm promises to have widespread applications, beyond biological systems. The source code for NETGEM is available from https://github.com/vjethava/NETGEM
Resumo:
In this note, a simplified procedure based on energy consideration, has been developed, for the solution of steady-state vibration of a system with combined viscous and Coulomb friction damping, subjected to frequency in dependent and frequency dependent excitation, which yields results essentially same as the exact solution. The proposed method uses results essentially same as the exact solution. The proposed method uses equivalent damping which assumes that if the damping in a system is small, the total damping effect can be represented by that of an equivalent damper.
Resumo:
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded DSP is complex and usually custom designed with multiple banks of single-ported or dual ported on-chip scratch pad memory and multiple banks of off-chip memory. Building software for such large complex memories with many of the software components as individually optimized software IPs is a big challenge. In order to obtain good performance and a reduction in memory stalls, the data buffers of the application need to be placed carefully in different types of memory. In this paper we present a unified framework (MODLEX) that combines different data layout optimizations to address the complex DSP memory architectures. Our method models the data layout problem as multi-objective genetic algorithm (GA) with performance and power being the objectives and presents a set of solution points which is attractive from a platform design viewpoint. While most of the work in the literature assumes that performance and power are non-conflicting objectives, our work demonstrates that there is significant trade-off (up to 70%) that is possible between power and performance.
Resumo:
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.
Resumo:
In an approach directed toward a tashironin based complex natural product, efficacy of the singlet oxygen mediated [4+2]-cycloaddition to a tetracyclic cyclopentadiene has been evaluated to install the key cis-1,4-dihydroxy functionality. (C) 2011 Elsevier Ltd. All rights reserved.
Resumo:
Distributed space-time block codes (DSTBCs) from complex orthogonal designs (CODs) (both square and nonsquare), coordinate interleaved orthogonal designs (CIODs), and Clifford unitary weight designs (CUWDs) are known to lose their single-symbol ML decodable (SSD) property when used in two-hop wireless relay networks using amplify and forward protocol. For such networks, in this paper, three new classes of high rate, training-symbol embedded (TSE) SSD DSTBCs are constructed: TSE-CODs, TSE-CIODs, and TSE-CUWDs. The proposed codes include the training symbols inside the structure of the code which is shown to be the key point to obtain the SSD property along with the channel estimation capability. TSE-CODs are shown to offer full-diversity for arbitrary complex constellations and the constellations for which TSE-CIODs and TSE-CUWDs offer full-diversity are characterized. It is shown that DSTBCs from nonsquare TSE-CODs provide better rates (in symbols per channel use) when compared to the known SSD DSTBCs for relay networks. Important from the practical point of view, the proposed DSTBCs do not contain any zeros in their codewords and as a result, antennas of the relay nodes do not undergo a sequence of switch on/off transitions within every codeword, and, thus, avoid the antenna switching problem.
Resumo:
Benzocyclobutene (BCB) has been proposed as a board level dielectric for advanced system-on-package (SOP) module primarily due to its attractive low-loss (for RF application) and thin film (for high density wiring) properties. Realization of embedded resistors on low loss benzocyclobutene (dielectric loss ~0.0008 at > 40 GHz) has been explored in this study. Two approaches, viz, foil transfer and electroless plating have been attempted for deposition of thin film resistors on benzocyclobutene (BCB). Ni-P alloys were plated using conventional electroless plating, and NiCr and NiCrAlSi foils were used for the foil transfer process. This paper reports NiP and NiWP electroless plated embedded resistors on BCB dielectric for the first time in the literature
Resumo:
This paper deals with surface profilometry, where we try to detect a periodic structure, hidden in randomness using the matched filter method of analysing the intensity of light, scattered from the surface. From the direct problem of light scattering from a composite rough surface of the above type, we find that the detectability of the periodic structure can be hindered by the randomness, being dependent on the correlation function of the random part. In our earlier works, we had concentrated mainly on the Cauchy-type correlation function for the rough part. In the present work, we show that this technique can determine the periodic structure of different kinds of correlation functions of the roughness, including Cauchy, Gaussian etc. We study the detection by the matched filter method as the nature of the correlation function is varied.