A Hybrid Multilevel Inverter System Based on Dodecagonal Space Vectors for Medium Voltage IM Drives

Dodecagonal (12-sided) space vector pulsewidth modulation (PWM) schemes are characterized by the complete absence of (6n +/- 1)th-order harmonics (for odd n) in the phase voltages, within the linear modulation range and beyond, including over-modulation. This paper presents a new topology suitable for the realization of such multilevel inverter schemes for induction motor (IM) drives, by cascading two-level inverters with flying-capacitor-inverter fed floating H-bridge cells. Now, any standard IM may be used to get the dodecagonal operation which hitherto was possible only with open-end winding IM. To minimize the current total harmonic distortion (THD), a strategy for synchronous PWM is also proposed. It is shown that the proposed method is capable of obtaining better THD figures, compared to conventional dodecagonal schemes. The topology and the PWM strategy are validated through analysis and subsequently verified experimentally.

Operand Isolation Circuits with Reduced Overhead for Low Power Data-Path Design

Dynamic power dissipation due to redundant switching is an important metric in data-path design. This paper focuses on the use of ingenious operand isolation circuits for low power design. Operand isolation attempts to reduce switching by clamping or latching the output of a first level of combinational circuit. This paper presents a novel method using power supply switching wherein both PMOS and NMOS stacks of a circuit are connected to the same power supply. Thus, the output gets clamped or latched to the power supply value with minimal leakage. The proposed circuits make use of only two transistors to clamp the entire Multiple Input Multiple Output (MIMO) block. Also, the latch-based designs have higher drive strength in comparison to the existing methods. Simulation results have shown considerable area reduction in comparison to the existing techniques without increasing timing overhead.

Flexible implementation of power system corrective topology control

This paper proposes a novel decision making framework for optimal transmission switching satisfying the AC feasibility, stability and circuit breaker (CB) reliability requirements needed for practical implementation. The proposed framework can be employed as a corrective tool in day to day operation planning scenarios in response to potential contingencies. The switching options are determined using an efficient heuristic algorithm based on DC optimal power flow, and are presented in a multi-branch tree structure. Then, the AC feasibility and stability checks are conducted and the CB condition monitoring data are employed to perform a CB reliability and line availability assessment. Ultimately, the operator will be offered multiple AC feasible and stable switching options with associated benefits. The operator can use this information, other operating conditions not explicitly considered in the optimization, and his/her own experience to implement the best and most reliable switching action(s). The effectiveness of the proposed approach is validated on the IEEE-118 bus test system. (C) 2015 Elsevier B.V. All rights reserved.

Analysis of sine-triangle and zero-sequence injection modulation schemes for split-phase induction motor drive

A split-phase induction motor is fed from two three-phase voltage source inverters for speed control. This study analyses carrier-comparison based pulse width modulation (PWM) schemes for a split-phase motor drive, from a space-vector perspective. Sine-triangle PWM, one zero-sequence injection PWM where the same zero-sequence signal is used for both the inverters, and another zero-sequence injection PWM where different zero-sequence signals are employed for the two inverters are considered. The set of voltage vectors applied, the sequence in which the voltage vectors are applied, and the resulting current ripple vector are analysed for all the PWM methods. Besides all the PWM methods are compared in terms of dc bus utilisation. For the same three-phase sine reference, the PWM method with different zero-sequence signals for the two inverters is found to employ a set of vectors different from the other methods. Both analysis and experimental results show that this method results in lower total harmonic distortion and higher dc bus utilisation than the other two PWM methods.

A DC-link Capacitor Voltage Balancing with CMV Elimination using only the Switching State Redundancies for a Reduced Switch Count Multi-Level Inverter fed IM Drive

Common mode voltage (CMV) variations in PWM inverter-fed drives generate unwanted shaft and bearing current resulting in early motor failure. Multilevel inverters reduce this problem to some extent, with higher number of levels. But the complexity of the power circuit increases with an increase in the number of inverter voltage levels. In this paper a five-level inverter structure is proposed for open-end winding induction motor (IM) drives, by cascading only two conventional two-level and three-level inverters, with the elimination of the common mode voltage over the entire modulation range. The DC link power supply requirement is also optimized by means of DC link capacitor voltage balancing, with PWM control., using only inverter switching state redundancies. The proposed power circuit gives a simple power bits structure.

A simple firing delay control circuit for bridge converters

A simple ramp control firing circuit, suitable for use with fully controlled, line-commutated thyristor bridge circuits, is discussed here. This circuit uses very few components and generates the synchronized firing pulses in a simple way. It operates from a single 15 V Supply and has an inherent pulse inhibit facility. This circuit provides the synchronized firing pulses for both thyristors of the same limb in a bridge. To ensure reliability, wide triggering pulses are used, which are modulated to pass through the pulse transformers1 and demodulated before being fed to the thyristor gates. The use of throe such circuits only for a three-phase bridge is discussed.

Protection and Switching-Aid Networks for Transistor Bridge Inverters

The present trend in the industry is towards the use of power transistors in the development of efficient Pulsewidth Modulated (PWM) inverters, because of their operation at high frequency, simplicity of turn-off, and low commutation losses compared to the technology using thyristors. But the protection of power transistors, minimization of switching power loss, and design of base drive circuit are very important for a reliable operation of the system. The requirements, analysis, and a simplified procedure for calculation of the switching-aid network components are presented. The transistor is protected against short circuit using a modified autoregulated and autoprotection drive circuit. The experimental results show that the switching power loss and voltage stress in the device can be reduced by suitable choice of the switching-aid network component values.

A simple firing delay control circuit for bridge converters

A simple ramp control firing circuit, suitable for use with fully controlled, line-commutated thyristor bridge circuits, is discussed here. This circuit uses very few components and generates the synchronized firing pulses in a simple way. It operates from a single 15 V Supply and has an inherent pulse inhibit facility. This circuit provides the synchronized firing pulses for both thyristors of the same limb in a bridge. To ensure reliability, wide triggering pulses are used, which are modulated to pass through the pulse transformers1 and demodulated before being fed to the thyristor gates. The use of throe such circuits only for a three-phase bridge is discussed.

Compact fiber Bragg grating dynamic strain sensor cum broadband thermometer for thermally unstable ambience

An instrument for simultaneous measurement of dynamic strain and temperature in a thermally unstable ambience has been proposed, based on fiber Bragg grating technology. The instrument can function as a compact and stand-alone broadband thermometer and a dynamic strain gauge. It employs a source wavelength tracking procedure for linear dependence of the output on the measurand, offering high dynamic range. Two schemes have been demonstrated with their relative merits. As a thermometer, the present instrumental configuration can offer a linear response in excess of 500 degrees C that can be easily extended by adding a suitable grating and source without any alteration in the procedure. Temperature sensitivity is about 0.06 degrees C for a bandwidth of 1 Hz. For the current grating, the upper limit of strain measurement is about 150 mu epsilon with a sensitivity of about 80 n epsilon Hz(-1/2). The major source of uncertainty associated with dynamic strain measurement is the laser source intensity noise, which is of broad spectral band. A low noise source device or the use of optical power regulators can offer improved performance. The total harmonic distortion is less than 0.5% up to about 50 mu epsilon, 1.2% at 100 mu epsilon and about 2.3% at 150 mu epsilon. Calibrated results of temperature and strain measurement with the instrument have been presented. Traces of ultrasound signals recorded by the system at 200 kHz, in an ambience of 100-200 degrees C temperature fluctuation, have been included. Also, the vibration spectrum and engine temperature of a running internal combustion engine has been recorded as a realistic application of the system.

Linear transconductor with flipped voltage follower in 130 nm CMOS

This paper presents a modified design method for linear transconductor circuit in 130 nm CMOS technology to improve linearity, robustness against process induced threshold voltage variability and reduce harmonic distortion. Source follower in the adaptively biased differential pair (ABDP) linear transconductor circuit is replaced with flipped voltage follower to improve the efficiency of the tail current source, which is connected to a conventional differential pair. The simulation results show the performance of the modified circuit also has better speed, noise performance and common mode rejection ratio compared to the ABDP circuit.

A Multilevel inverter structure with cascaded two level and three level inverters for IM drive with CMV elimination and DC link capacitor voltage balancing

Common mode voltage (CMV) variations in PWM inverter-fed drives generate unwanted shaft and bearing current resulting in early motor failure. Multilevel inverters reduce this problem to some extent, with higher number of levels. But the complexity of the power circuit increases with an increase in the number of inverter voltage levels. In this paper a five-level inverter structure is proposed for open-end winding induction motor (IM) drives, by cascading only two conventional two-level and three-level inverters, with the elimination of the common mode voltage over the entire modulation range. The DC link power supply requirement is also optimized by means of DC link capacitor voltage balancing, with PWM control, using only inverter switching state redundancies. The proposed power circuit gives a simple power bus structure.

An Overmodulation Scheme for Vector Controlled Induction Motor Drives

This paper presents an algorithm for control of line side voltage of a voltage source inverter upto six-step mode. This is a modified version of an existing overmodulation algorithm. The modified algorithm maintains proportionality between the reference voltage and the output fundamental voltage, and also reduces the computational effort required for implementation, while resulting in a marginally higher harmonic distortion. An estimation method is proposed for calculation of lower order ripple current. This estimation method is applied to a sensorless vector controlled induction motor drive to improve the performance of the drive during overmodulation.

Performance of telecommunication modules to 0.5µS-100kHz ring wave surges

This paper presents an experimental investigations performed on various electronic components used in telecommunication networks and those used in avionics for the ring wave surge voltages. IEEE Std C 62.41.1-2002 specifies a stringent requirement of waveforms to be applied for the evaluation of telecom components. To meet the necessary requirements in the absence of commercial equipment for generating the required waveforms, special efforts were made to fabricate a ring wave surge generator as per prescribed standards. The developed surge generator is capable of delivering an output of 0.5 mu s-100kHz which meets the requirements of telecom standards prescribed for evaluation of various modules used in low voltage ac power circuits used in communication networks. The results of the experimental investigations obtained on various modules used in communication networks are presented.

Analysis of Bandwidth-Unit-Vector-Distortion Tradeoff in PLL During Abnormal Grid Conditions

Phase-locked loops (PLLs) are necessary in applications which require grid synchronization. Presence of unbalance or harmonics in the grid voltage creates errors in the estimated frequency and angle of a PLL. The error in estimated angle has the effect of distorting the unit vectors generated by the PLL. In this paper, analytical expressions are derived which determine the error in the phase angle estimated by a PLL when there is unbalance and harmonics in the grid voltage. By using the derived expressions, the total harmonic distortion (THD) and the fundamental phase error of the unit vectors can be determined for a given PLL topology and a given level of unbalance and distortion in the grid voltage. The accuracy of the results obtained from the analytical expressions is validated with the simulation and experimental results for synchronous reference frame PLL (SRF-PLL). Based on these expressions, a new tuning method for the SRF-PLL is proposed which quantifies the tradeoff between the unit vector THD and the bandwidth of the SRF-PLL. Using this method, the exact value of the bandwidth of the SRF-PLL can be obtained for a given worst case grid voltage unbalance and distortion to have an acceptable level of unit vector THD. The tuning method for SRF-PLL is also validated experimentally.

Average Modelling of a Voltage Source Inverter with Dead-Time in a Synchronous Reference Frame

Voltage source inverters are an integral part of renewable power sources and smart grid systems. Computationally efficient and fairly accurate models for the voltage source inverter are required to carry out extensive simulation studies on complex power networks. Accuracy requires that the effect of dead-time be incorporated in the inverter model. The dead-time is essentially a short delay introduced between the gating pulses to the complementary switches in an inverter leg for the safety of power devices. As the modern voltage source inverters switch at fairly high frequencies, the dead-time significantly influences the output fundamental voltage. Dead-time also causes low-frequency harmonic distortion and is hence important from a power quality perspective. This paper studies the dead-time effect in a synchronous dq reference frame, since dynamic studies and controller design are typically carried out in this frame of reference. For the sake of computational efficiency, average models are derived, incorporating the dead-time effect, in both RYB and dq reference frames. The average models are shown to consume less computation time than their corresponding switching models, the accuracies of the models being comparable. The proposed average synchronous reference frame model, including effect of dead-time, is validated through experimental results.