Generating synchronizable test sequences based on finite-statemachine with distributed ports

In the area of testing communication systems, the interfaces between systems to be tested and their testers have great impact on test generation and fault detectability. Several types of such interfaces have been standardized by the International Standardization Organization (ISO). A general distributed test architecture, containing distributed interfaces, has been presented in the literature for testing distributed systems based on the Open Distributing Processing (ODP) Basic Reference Model (BRM), which is a generalized version of ISO distributed test architecture. We study in this paper the issue of test selection with respect to such an test architecture. In particular, we consider communication systems that can be modeled by finite state machines with several distributed interfaces, called ports. A test generation method is developed for generating test sequences for such finite state machines, which is based on the idea of synchronizable test sequences. Starting from the initial effort by Sarikaya, a certain amount of work has been done for generating test sequences for finite state machines with respect to the ISO distributed test architecture, all based on the idea of modifying existing test generation methods to generate synchronizable test sequences. However, none studies the fault coverage provided by their methods. We investigate the issue of fault coverage and point out a fact that the methods given in the literature for the distributed test architecture cannot ensure the same fault coverage as the corresponding original testing methods. We also study the limitation of fault detectability in the distributed test architecture.

Recovery of copper from vanadiferrous magnetite ore of Masanikere area, Shimoga district

Studies have been carried out to recover copper from vanadiferrous magnetite ores by a novel reaction with lime in the presence of water vapour. The ore, mixed with different proportions of lime, has been roasted in the presence of steam. The roasted product is either directly leached with dilute mineral acids or subjected to magnetic separation and then leached. The effect of various parameters such as amount of lime added, temperature and duration of roasting and time of leaching on the recovery of copper has been investigated. The results indicate that over 90% copper could be recovered under optimum conditions of roasting and leaching.

Decentralized Sustainable Energy Planning of Tumkur District, India

Present work shows the feasibility of decentralized energy options for the Tumkur district in India. Decentralized energy planning (DEP) involves scaling down energy planning to subnational or regional scales. The important aspect of the energy planning at decentralized level would be to prepare an area-based DEP to meet energy needs and development of alternate energy sources at least-cost to the economy and environment. The geographical coverage and scale reflects the level at which the analysis takes place, which is an important factor in determining the structure of models. In the present work, DEP modeling under different scenarios has been carried out for Tumkur district of India for the year 2020. DEP model is suitably scaled for obtaining the optimal mix of energy resources and technologies using a computer-based goal programming technique. The rural areas of the Tumkur district have different energy needs. Results show that electricity needs can be met by biomass gasifier technology, using biomass feedstock produced by allocating only 12% of the wasteland in the district at 8 t/ha/yr of biomass productivity. Surplus electricity can be produced by adopting the option of biomass power generation from energy plantations. The surplus electricity generated can be supplied to the grid. The sustainable development scenario is a least cost scenario apart from promoting self-reliance, local employment, and environmental benefits. (C) 2010 American Institute of Chemical Engineers Environ Prog, 30: 248-258, 2011

Limit Laws for Coverage in Backbone-Sensor Networks

We study the coverage in sensor networks having two types of nodes, sensor and backbone nodes. Each sensor is capable of transmitting information over relatively small distances. The backbone nodes collect information from the sensors. This information is processed and communicated over an ad-hoc network formed by the backbone nodes,which are capable of transmitting over much larger distances. We consider two modes of deployment of sensors, one a Poisson-Poisson cluster model and the other a dependently-thinned Poisson point process. We deduce limit laws for functionals of vacancy in both models using properties of association for random measures.

Lamb wave based identification and parameter estimation of corrosion in metallic plate structure using a circular PWAS array

A circular array of Piezoelectric Wafer Active Sensor (PWAS) has been employed to detect surface damages like corrosion using lamb waves. The array consists of a number of small PWASs of 10 mm diameter and 1 mm thickness. The advantage of a circular array is its compact arrangement and large area of coverage for monitoring with small area of physical access. Growth of corrosion is monitored in a laboratory-scale set-up using the PWAS array and the nature of reflected and transmitted Lamb wave patterns due to corrosion is investigated. The wavelet time-frequency maps of the sensor signals are employed and a damage index is plotted against the damage parameters and varying frequency of the actuation signal (a windowed sine signal). The variation of wavelet coefficient for different growth of corrosion is studied. Wavelet coefficient as function of time gives an insight into the effect of corrosion in time-frequency scale. We present here a method to eliminate the time scale effect which helps in identifying easily the signature of damage in the measured signals. The proposed method becomes useful in determining the approximate location of the corrosion with respect to the location of three neighboring sensors in the circular array. A cumulative damage index is computed for varying damage sizes and the results appear promising.

Aromatic, microporous polymer networks with high surface area generated in Friedel-Crafts-type polycondensations

A series of novel, microporous polymer networks (MPNs) have been generated in a simple, acid catalysed Friedel-Crafts-type self-condensation of A(2)B(2)- and A(2)B(4)-type fluorenone monomers. Two A2B4-type monomers with 2,7-bis(N, N-diphenylamino) A or 2,7-bis [4-(N, N-diphenylamino) phenyl] D substitution of the fluorenone cores lead to MPNs with high S(BET) surface areas of up to 1400 m(2) g(-1). Two MPNs made of binary monomer mixtures showed the highest Brunauer-Emmett-Teller (BET) surface areas S(BET) of our series (SBET of up to 1800 m(2) g(-1)) after washing the powdery samples with supercritical carbon dioxide. Total pore volumes of up to 1.6 cm(3) g(-1) have been detected. It is observed that the substitution pattern of the monomers is strongly influencing the resulting physicochemical properties of the microporous polymer networks (MPNs).

Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing

Transfer function coefficients (TFC) are widely used to test linear analog circuits for parametric and catastrophic faults. This paper presents closed form expressions for an upper bound on the defect level (DL) and a lower bound on fault coverage (FC) achievable in TFC based test method. The computed bounds have been tested and validated on several benchmark circuits. Further, application of these bounds to scalable RC ladder networks reveal a number of interesting characteristics. The approach adopted here is general and can be extended to find bounds of DL and FC of other parametric test methods for linear and non-linear circuits.

INTACTE: An Interconnect Area, Delay, and Energy Estimation Tool for Microarchitectural Explorations

Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters. Hence these models are hard to use directly to make high level microarchitectural trade-offs in the initial exploration phase of a design. In this paper, we propose INTACTE, a tool that can be used by architects toget reasonably accurate interconnect area, delay, and power estimates based on a few architecture level parameters for the interconnect such as length, width (in number of bits), frequency, and latency for a specified technology and voltage. The tool uses well known models of interconnect delay and energy taking into account the wire pitch, repeater size, and spacing for a range of voltages and technologies.It then solves an optimization problem of finding the lowest energy interconnect design in terms of the low level circuit parameters, which meets the architectural constraintsgiven as inputs. In addition, the tool also provides the area, energy, and delay for a range of supply voltages and degrees of pipelining, which can be used for micro-architectural exploration of a chip. The delay and energy models used by the tool have been validated against low level circuit simulations. We discuss several potential applications of the tool and present an example of optimizing interconnect design in the context of clustered VLIW architectures. Copyright 2007 ACM.

Speed and Area Optimized Implementation of H.264 8X8 DCT Transform and Quantizer

H.264 is a video codec standard which delivers high resolution video even at low bit rates. To provide high throughput at low bit rates hardware implementations are essential. In this paper, we propose hardware implementations for speed and area optimized DCT and quantizer modules. To target above criteria we propose two architectures. First architecture is speed optimized which gives a high throughput and can meet requirements of 4096x2304 frame at 30 frames/sec. Second architecture is area optimized and occupies 2009 LUTs in Altera’s stratix-II and can meet the requirements of 1080HD at 30 frames/sec.

An Area-Efficient Noise-Adaptive Neural Amplifier in 130 nm CMOS Technology

Chronic recording of neural signals is indispensable in designing efficient brain–machine interfaces and to elucidate human neurophysiology. The advent of multichannel micro-electrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system can vary over time due to change in electrode–neuron distance and background noise. We propose a neural amplifier in UMC 130 nm, 1P8M complementary metal–oxide–semiconductor (CMOS) technology. It can be biased adaptively from 200 nA to 2 $mu{rm A}$, modulating input referred noise from 9.92 $mu{rm V}$ to 3.9 $mu{rm V}$. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier and obviates the need of large input capacitance. The amplifier achieves a noise efficiency factor of 2.58. The amplifier can pass signal from 5 Hz to 7 kHz and the bandwidth of the amplifier can be tuned for rejecting low field potentials (LFP) and power line interference. The amplifier achieves a mid-band voltage gain of 37 dB. In vitro experiments are performed to validate the applicability of the neural low noise amplifier in neural recording systems.

Fuzzy logic based TCSC supplementary controller for damping of inter area oscillations in power system

This paper describes an application of a FACTS supplementary controller for damping of inter area oscillations in power systems. A fuzzy logic controller is designed to regulate a thyristor controlled series capacitor (TCSC) in a multimachine environment to produce additional damping in the system. Simultaneous application of the excitation controller and proposed controller is also investigated. Simulation studies have been done with different types of disturbances and the results are shown to be consistent with the expected performance of the supplementary controller.

Location Area Planning Using Simulated Annealing With A New Solution Representation

Location area planning problem is to partition the cellular/mobile network into location areas with the objective of minimizing the total cost. This partitioning problem is a difficult combinatorial optimization problem. In this paper, we use the simulated annealing with a new solution representation. In our method, we can automatically generate different number of location areas using Compact Index (CI) to obtain the optimal/best partitions. We compare the results obtained in our method with the earlier results available in literature. We show that our methodology is able to perform better than earlier methods.