A Harmonic Suppression Scheme for Open-End Winding Split-Phase IM Drive Using Capacitive Filters for the Full Speed Range

Voltage source inverter (VSI)-fed six-phase induction motor (IM) drives have high 6n +/- 1, n = odd-order harmonic currents. This is because these currents, driven by the corresponding harmonic voltages in the inverter output, are limited only by the stator leakage impedance, as these harmonics are absent in the back electromotive force of the motor. To suppress the harmonic currents, either bulky inductive harmonic filters or complex pulsewidth modulation (PWM) techniques have to be used. This paper proposes a harmonic elimination scheme using switched capacitor filters for a VSI-fed split-phase IM drive. Two 3-phase inverters fed from capacitors are used on the open-end side of the motor to suppress 6n +/- 1, n = odd-order harmonics. A PWM scheme that can suppress the harmonics as well as balance the capacitor voltage is also proposed. The capacitor fed inverters are switched so that the fundamental voltage is not affected, and the fundamental power is always drawn from the main inverters. The proposed scheme is verified with a detailed experimental study. The effectiveness of the scheme is demonstrated by comparing the results with those obtained by disabling the capacitor fed inverters.

Harmonic analysis of DC capacitor current in sinusoidal and space-vector modulated neutral-point-clamped inverters

The voltage ripple and power loss in the DC-capacitor of a voltage source inverter depend on the harmonic currents flowing through the capacitor. This paper presents a double Fourier series based analysis of the harmonic contents of the DC capacitor current in a three-level neutral-point clamped (NPC) inverter, modulated with sine-triangle pulse-width modulation (SPWM) or conventional space vector pulse-width modulation (CSVPWM) schemes. The analytical results are validated experimentally on a 3-kVA three-level inverter prototype. The capacitor current in an NPC inverter has a periodicity of 120(a similar to) at the fundamental or modulation frequency. Hence, this current contains third-harmonic and triplen-frequency components, apart from switching frequency components. The harmonic components vary with modulation index and power factor for both PWM schemes. The third harmonic current decreases with increase in modulation index and also decreases with increase in power factor in case of both PWM methods. In general, the third harmonic content is higher with SPWM than with CSVPWM at a given operating condition. Also, power loss and voltage ripple in the DC capacitor are estimated for both the schemes using the current harmonic spectrum and equivalent series resistance (ESR) of the capacitor.

Theoretical and Experimental Evaluation of Pulsating Torque Produced by Induction Motor Drives Controlled With Advanced Bus-Clamping Pulsewidth Modulation

This paper investigates possible reduction of pulsating torque in open-loop and vector-controlled induction motor drives through deployment of certain advanced bus-clamping pulsewidth modulation (ABCPWM) method. Toward this goal, a simple and machine-independent method is proposed to analyze the torque harmonic spectrum of a voltage source inverter fed induction motor, operated with any real-time pulsewidth modulation (PWM) method. The analytically evaluated torque harmonic spectra, pertaining to conventional space vector PWM (CSVPWM), bus-clamping PWM (BCPWM), and ABCPWM, are validated through simulation and experimental results. Theoretical and experimental studies bring out the superiority of the ABCPWM in terms of torque harmonics over CSVPWM and BCPWM. The magnitude of the dominant torque harmonic with the ABCPWM scheme is shown to be significantly lower than that with CSVPWM, over a wide range of speed. The rms torque ripple (i.e., total rms value of all harmonic torques) is lower with ABCPWM than with BCPWM over the entire range of speed.

A Front end Switched Rectifier DC Source for Neutral Point Balancing of A NPC Three-Level Inverter for The Full Modulation Range

A switched DC voltage three level NPC is proposed in this paper to eliminate capacitor balancing problems in conventional three-level Neutral Point Clamped (NPC) inverter. The proposed configuration requires only one DC link with a voltage V-dc/2, where V-dc is the DC link voltage in a onventional NPC inverter. To get rated DC link voltage (V-dc), the voltage source is alternately onnected in parallel to one of the two series capacitors using two switches and two diodes with device voltage rating of V-dc/2. The frequency at which the voltage source is switched is independent and will not affect the operation of NPC inverter. The switched voltage source in this configuration balances the capacitors automatically. The proposed configuration can also be used as a conventional two level inverter in lower modulation range, thereby increases the reliability of the drive system. A space vector based PWM scheme is used to verify this proposed topology.

Neutral-point balancing of neutral-point-clamped three-level inverter with a front end switched rectifier DC source for the full modulationn range

A switched rectifier DC voltage source three-level neutral-point-clamped (NPC) converter topology is proposed here to alleviate the inverter from capacitor voltage balancing in three-level drive systems. The proposed configuration requires only one DC link with a voltage of half of that needed in a conventional NPC inverter. To obtain a rated DC link voltage, the rectifier DC source is alternately connected in parallel to one of the two series capacitors using two switches and two diodes with device voltage ratings of half the total DC bus voltage. The frequency at which the voltage source is switched is independent of the inverter and will not affect its operation since the switched voltage source in this configuration balances the capacitors automatically. The proposed configuration can also be used as a conventional two-level inverter in the lower modulation index range, thereby increasing the reliability of the drivesystem. A space-vector-based PWM scheme is used to verify this proposed topology on a laboratory system.

A Hybrid Five-Level Inverter With Common-Mode Voltage Elimination Having Single Voltage Source for IM Drive Applications

A new hybrid five-level inverter topology with common-mode voltage (CMV) elimination for induction motor drive is proposed in this paper. This topology has only one dc source, and different voltage levels are generated by using this voltage source along with floating capacitors charged to asymmetrical voltage levels. The pulsewidth modulation (PWM) scheme employed in this topology balances the capacitor voltages at the required levels at any power factor and modulation index while eliminating the CMV. This inverter has good fault-tolerant capability as it can be operated in three-or two-level mode with CMV elimination, in case of any failure in the H-bridges. More voltage levels with CMV elimination can be realized from this topology but only in a limited range of modulation index and power factor. Extensive simulation is done to validate the PWM technique for CMV elimination and balancing of the capacitor voltages. The experimental verification of the proposed inverter-fed induction motor is carried out in the linear modulation and overmodulation regions. The steady-state and transient operations of the drive are verified. The dynamics of the capacitor voltage balancing is also tested. The experimental results demonstrate that the proposed topology can be considered for industrial drive applications.

A Reduced Device-Count Hybrid Multilevel Inverter Topology with single DC Source and Improved Fault Tolerance

A new hybrid multilevel power converter topology is presented in this paper. The proposed power converter topology uses only one DC source and floating capacitors charged to asymmetrical voltage levels, are used for generating different voltage levels. The SVPWM based control strategy used in this converter maintains the capacitor voltages at the required levels in the entire modulation range including the over-modulation region. For the voltage levels: nine and above, the number of components required in the proposed topology is significantly lower, compared to the conventional multilevel inverter topologies. The number of capacitors required in this topology reduces drastically compared to the conventional flying capacitor topology, when the number of levels in the inverter output increases. This topology has better fault tolerance, as it is capable of operating with reduced number of levels, in the entire modulation range, in the event of any failure in the H-bridges. The transient as well as the steady state performance of the nine-level version of the proposed topology is experimentally verified in the entire modulation range including the over-modulation region.

Reduced common-mode voltage operation of a new seven-level hybrid multilevel inverter topology with a single DC voltage source

In this study, analysis of extending the linear modulation range of a zero common-mode voltage (CMV) operated n-level inverter by allowing reduced CMV switching is presented. A new hybrid seven-level inverter topology with a single DC supply is also presented in this study and inverter operation for zero and reduced CMV is analysed. Each phase of the inverter is realised by cascading two three-level flying capacitor inverters with a half-bridge module in between. Proposed inverter topology is operated with zero CMV for modulation index <86% and is operated with a CMV magnitude of V-dc/18 to extend the modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilising the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology.

A New PWM Control Method for Three-Phase Autosequentially Commutated Current Source Inverters

A new current pulsewidth modulation (PWM) method is presented which uses the principle of creating zero three-phase currents at selected instants of time, through which the load current harmonic content can be controlled along with the magnitude of its fundamental content. This gives rise to reduction of motor torque ripples through the selection of suitable PWM patterns and a fast current control in the inverter by varying the pulsewidths of the PWM pattern. Under this new PWM mode of operation, the autosequentially commutated inverter (ASCI) circuit can be modified easily so that a higher number of pulses can be accomodated within a half-cycle, compared to the normal ASCI circuit. The experimental oscillograms verify the effectiveness of the new PWM method.

A Hardware Grid Simulator to Test Grid-Connected Inverter Systems.

Grid-connected systems when put to use at the site would experience scenarios like voltage sag, voltage swell, frequency deviations and unbalance which are common in the real world grid. When these systems are tested at laboratory, these scenarios do not exist and an almost stiff voltage source is what is usually seen. But, to qualify the grid-connected systems to operate at the site, it becomes essential to test them under the grid conditions mentioned earlier. The grid simulator is a hardware that can be programmed to generate some of the typical conditions experienced by the grid-connected systems at site. It is an inverter that is controlled to act like a voltage source in series with a grid impedance. The series grid impedance is emulated virtually within the inverter control rather than through physical components, thus avoiding the losses and the need for bulky reactive components. This paper describes the design of a grid simulator. Control implementation issues are highlighted in the experimental results.

Synthesis and characterization of metal substituted AlxCr1-x(acetylacetonate)(3) single-source precursors for their application to MOCVD of thin films

A detailed study, involving the synthesis of a single-source precursor containing two metal ions sharing the same crystallographic site, has been undertaken to elucidate the use of such a single-source precursor in a CVD process for growing thin films of oxides comprising these two metals, ensuring a uniform composition and distribution of metal ions. The substituted complexes Cr1-xAlx(acac)(3), where acac = acetyl-acetonate, have been prepared by a co-synthesis method, and characterized using UV-Vis spectroscopy. TGA/DTA measurements, and single crystal X-ray diffraction at low temperature. All the studied compositions crystallize in the monoclinic space group P2(1)/c with Z = 4 in the unit cell. It was observed that the ratio (Al:Cr) of the site occupancy for the metal ions, obtained from single crystal refinement, is in agreement with the results obtained from complexometric titrations. All the solid state structures have the metal in an octahedral environment forming six-membered chelate rings. M-O acac bond lengths and disorder in the terminal carbon have been studied in detail for these substituted metal-organic complexes. One composition among these was chosen to evaluate their suitability as a single-source precursor in a LPMOCVD process (low-pressure metal-organic chemical vapour deposition) for the deposition of a substituted binary metal oxide thin film. The resulting thin films were characterized by X-ray diffraction, scanning electron microscopy, and infrared spectroscopy. (C) 2010 Elsevier Ltd. All rights reserved.

Performance Optimization of Induction Motor-Pump System Using Photovoltaic Energy Source

The optimization of a photovoltaic pumping system based on an induction motor driven pump that is powered by a solar array is presented in this paper. The motor-pump subsystem is analyzed from the point of view of optimizing the power requirement of the induction motor, which has led to an optimum u-f relationship useful in controlling the motor. The complete pumping system is implemented using a dc-dc converter, a three-phase inverter, and an induction motor-pump set. The dc-dc converter is used as a power conditioner and its duty cycle is controlled so as to match the load to the array. A microprocessor-based controller is used to carry out the load-matching.

On the Compressibility of non-Abelian-Group Sources in a Distributed Source Coding Setting

We consider the problem of compression of a non-Abelian source.This is motivated by the problem of distributed function computation,where it is known that if one is only interested in computing a function of several sources, then one can often improve upon the compression rate required by the Slepian-Wolf bound. Let G be a non-Abelian group having center Z(G). We show here that it is impossible to compress a source with symbols drawn from G when Z(G) is trivial if one employs a homomorphic encoder and a typical-set decoder.We provide achievable upper bounds on the minimum rate required to compress a non-Abelian group with non-trivial center. Also, in a two source setting, we provide achievable upper bounds for compression of any non-Abelian group, using a non-homomorphic encoder.

A Five-Level Inverter Topology with Single-DC Supply by Cascading a Flying Capacitor Inverter and an H-Bridge

In this paper, a new three-phase, five-level inverter topology with a single-dc source is presented. The proposed topology is obtained by cascading a three-level flying capacitor inverter with a flying H-bridge power cell in each phase. This topology has redundant switching states for generating different pole voltages. By selecting appropriate switching states, the capacitor voltages can be balanced instantaneously (as compared to the fundamental) in any direction of the current, irrespective of the load power factor. Another important feature of this topology is that if any H-bridge fails, it can be bypassed and the configuration can still operate as a three-level inverter at its full power rating. This feature improves the reliability of the circuit. A 3-kW induction motor is run with the proposed topology for the full modulation range. The effectiveness of the capacitor balancing algorithm is tested for the full range of speed and during the sudden acceleration of the motor.