A Multilevel Inverter with Hexagonal and 12-sided Polygonal Space Vector Structure for Induction Motor Drive

This paper proposes a multilevel inverter which produces hexagonal voltage space vector structure in lower modulation region and a 12-sided polygonal space vector structure in the over-modulation region. Normal conventional multilevel inverter produces 6n +/- 1 (n=odd) harmonics in the phase voltage during over-modulation and in the extreme square wave mode operation. However, this inverter produces a 12-sided polygonal space vector location leading to the elimination of 6n 1 (n=odd) harmonics in over-modulation region extending to a final 12-step mode operation. The inverter consists of three conventional cascaded two level inverters with asymmetric dc bus voltages. The switching frequency of individual inverters is kept low throughout the modulation index. In the low speed region, hexagonal space phasor based PWM scheme and in the higher modulation region, 12-sided polygonal voltage space vector structure is used. Experimental results presented in this paper shows that the proposed converter is suitable for high power applications because of low harmonic distortion and low switching losses.

Space-Time Codes Achieving the DMD Tradeoff of the MIMO-ARQ Channel

For the quasi-static, Rayleigh-fading multiple-input multiple-output (MIMO) channel with n(t) transmit and n(r) receive antennas, Zheng and Tse showed that there exists a fundamental tradeoff between diversity and spatial-multiplexing gains, referred to as the diversity-multiplexing gain (D-MG) tradeoff. Subsequently, El Gamal, Caire, and Damen considered signaling across the same channel using an L-round automatic retransmission request (ARQ) protocol that assumes the presence of a noiseless feedback channel capable of conveying one bit of information per use of the feedback channel. They showed that given a fixed number L of ARQ rounds and no power control, there is a tradeoff between diversity and multiplexing gains, termed the diversity-multiplexing-delay (DMD) tradeoff. This tradeoff indicates that the diversity gain under the ARQ scheme for a particular information rate is considerably larger than that obtainable in the absence of feedback. In this paper, a set of sufficient conditions under which a space-time (ST) code will achieve the DMD tradeoff is presented. This is followed by two classes of explicit constructions of ST codes which meet these conditions. Constructions belonging to the first class achieve minimum delay and apply to a broad class of fading channels whenever n(r) >= n(t) and either L/n(t) or n(t)kslashL. The second class of constructions do not achieve minimum delay, but do achieve the DMD tradeoff of the fading channel for all statistical descriptions of the channel and for all values of the parameters n(r,) n(t,) L.

A simple firing delay control circuit for bridge converters

A simple ramp control firing circuit, suitable for use with fully controlled, line-commutated thyristor bridge circuits, is discussed here. This circuit uses very few components and generates the synchronized firing pulses in a simple way. It operates from a single 15 V Supply and has an inherent pulse inhibit facility. This circuit provides the synchronized firing pulses for both thyristors of the same limb in a bridge. To ensure reliability, wide triggering pulses are used, which are modulated to pass through the pulse transformers1 and demodulated before being fed to the thyristor gates. The use of throe such circuits only for a three-phase bridge is discussed.

A Pulsewidth Modulated Control of Induction Motor Drive Using Multilevel 12-Sided Polygonal Voltage Space Vectors

In this paper, a novel 12-sided polygonal space vector structure is proposed for an induction motor drive. The space vector pattern presented in this paper consists of two 12-sided concentric polygons with the outer polygon having a radius double the inner one. As compared to previously reported 12-sided polygonal space vector structures, this paper subdivides the space vector plane into smaller sized triangles. This helps in reducing the switching frequency of the inverters without deteriorating the output voltage quality. It also reduces the device ratings and dv/dt stress on the devices to half. At the same time, other benefits obtained from the existing 12-sided space vector structure, such as increased linear modulation range and complete elimination of 5th and 7th order harmonics in the phase voltage, are also retained in this paper. The space vector structure is realized by feeding an open-end induction motor with two conventional three-level neutral point clamped (NPC) inverters with asymmetric isolated dc link voltage sources. The neutral point voltage fluctuations in the three-level NPC inverters are eliminated by utilizing the switching state multiplicities for a space vector point. The pulsewidth modulation timings are calculated using sampled reference waveform amplitudes and are explained in detail in this paper. Experimental verification on a laboratory prototype shows that this configuration may be considered suitable for high power drives.